BQ25606 Datasheet, PDF (5/43 Pages) Texas Instruments – Standalone 3.0-A, Single Cell Battery Charger With 40V Over Voltage Protection Controller

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Terminal
Name
No.
STAT
5
19
SW
20
15
SYS
16
TS
11
VAC
1
VBUS
24
VSET
12
Thermal Pad
bq25606
(continued)
SLUSCK6 – MAY 2017
I/O Description
Open-drain interrupt output. Connect the STAT pin to a logic rail via 10-kΩ resistor. The STAT pin
indicates charger status.
DO Charge in progress: LOW
Charge complete or charger in SLEEP mode: HIGH
Charge suspend (fault response): BlinK at 1Hz
Switching node connecting to output inductor. Internally SW is connected to the source of the n-channel
P
HSFET and the drain of the n-channel LSFET. Connect the 0.047-μF bootstrap capacitor from SW to
BTST.
P
Converter output connection point. The internal current sensing resistor is connected between SYS and
BAT. Connect a 20 µF capacitor close to the SYS pin.
Temperature qualification voltage input to support JEITA profile. Connect a negative temperature
AI coefficient thermistor. Program temperature window with a resistor divider from REGN to TS to GND.
Charge suspends when TS pin voltage is out of range. Recommend 103AT-2 thermistor.
AI
Input voltage sensing. When VAC voltage is below ACOV threshold and above UVLO, external OVPFET
turns on. If exteral OVP is not used, This pin must be shorted to VBUS pin.
Charger input voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between
P
VBUS and PMID with VBUS on source. Place a 1-uF ceramic capacitor from VBUS to GND and place it
as close as possible to IC.
VSET pin sets default battery charge voltage in bq25606. Program battery regulation voltage with a
resistor pull-down from VSET to GND.
AI R_PD > 50kΩ (float pin) = 4.208 V
R_PD < 500Ω (short to GND) = 4.352 V
5kΩ < R_PD < 25kΩ = 4.400 V
Ground reference for the device that is also the thermal pad used to conduct heat from the device. This
P
connection serves two purposes. The first purpose is to provide an electrical ground connection for the
device. The second purpose is to provide a low thermal-impedance path from the device die to the PCB.
This pad should be tied externally to a ground plane.
Copyright © 2017, Texas Instruments Incorporated
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