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TLC320AC01C_15 Datasheet, PDF (49/92 Pages) Texas Instruments – Single-Supply Analog Interface Circuit | |||
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2V
SCLK
FSâ 0.8 V
tf(SCLK)
2V
0.8 V
td(CH-FL)
DOUTâ¡
D15
D14
D13
tr(SCLK)
td(CH-DOUT)
D12
D11
2V
td(CH-FH)
2V
D2
D1
D0
tsu(DIN)
DIN
D15
D14
D13
D12
D11
D2
D1
D0
th(DIN)
â The time between falling edges of two primary FS signals is the conversion period.
â¡ The data on DOUT are shifted out on the rising edge of the shift clock, and the data on DIN are shifted in on the falling
edge of the shift clock.
Figure 4 â 2. AIC Stand-Alone and Master-Mode Timing
2V
SCLK
§
FSâ
DOUTâ¡
D15
tf(SCLK)
2V
0.8 V
tr(SCLK)
td(CH-DOUT)
D14
D13
D12
D11
tc(SCLK)
2V
2V
D2
D1
D0
tsu(DIN)
DIN
D15
D14
D13
D12
D11
D2
D1
D0
th(DIN)
â The time between falling edges of two primary FS signals is the conversion period.
â¡ The data on DOUT are shifted out on the rising edge of the shift clock, and the data on DIN are shifted in on the falling
edge of the shift clock.
§ The high-to-low transition of FS must must occur within ±1/4 of a shift-clock period around the 2-V level of the shift clock
for the codec mode.
Figure 4 â 3. AIC Slave and Codec Emulation Mode
4â2
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