TLC320AC01C_15 Datasheet, PDF (19/92 Pages) Texas Instruments – Single-Supply Analog Interface Circuit

2.8 Required Minimum Number of MCLK Periods
Master with slave operation is summarized in the following sections.
2.8.1 TLC320AC01 AIC Master-Slave Summary
After initial setup and the master and slave frame syncs are separated, when secondary communication is
needed for a slave device, a 11 must be placed in the 2 LSBs of each primary data word for all devices in
the system, master and slave, by the host processor. In other words, all AICs must receive secondary frame
requests.
The host processor must issue the command by setting D01 and D00 to a 1 in the primary frame sync data
word of all devices. Then the master generates the master primary frame sync and, after the number of shift
clocks set by the FSD register value, the slave primary frame sync intervals. Then, after (B register value/2)
FCLK periods, the master secondary frame sync occurs first, and then the slave secondary frame sync
occurs. These are also rippled through the slave devices.
In other words, when a secondary communications interval is requested by the host processor as described
above:
1. The master outputs the master primary frame sync interval, and then the slave primary frame
sync intervals after the FSD register value number of shift clocks.
2. After (B register value/2) FCLK periods, the master then outputs the master secondary frame
sync interval, and after the FSD register value number of shift clocks, the slave secondary frame
sync intervals.
This sequence is shown in Figure 2–2.
The host must keep track of whether the master or a slave is then being addressed and also the number
of slave devices. The master always outputs a 00 in the last 2 bits of the DOUT word, and a slave always
outputs a 1 in the LSB of the DOUT word. This information allows the system to recognize a starting point
by interrogating the least significant bit of the DOUT word. If the LSB is 0, then that device is the master,
and the system is at the starting point.
Note: This identification always happens except in 16-bit mode when the 2 LSBs are not available
for identification purposes.
FSD Value
in SCLKs
(B Register Value/2) FCLK Periods
Sampling Period
Frame Sync
Sequence
Period Symbol MP
SP1
SP2
SPn
MS
SS1
SS2
SSn
MP
Periods shown: Each period must be a minimum of 16 SCLKs plus 2 additional SCLKs
MP
= Master Primary Period
SP1
= 1st Slave Primary Period
SP2
= 2nd Slave Primary Period
SPn
= nth Slave Primary Period
MS
= Master Secondary Period
SS1
= 1st Slave Secondary Period
SS2
= 2nd Slave Secondary Period
SSn = nth Slave Secondary Period
Figure 2–2. Timing Sequence
2–6