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TLC320AC01C_15 Datasheet, PDF (45/92 Pages) Texas Instruments – Single-Supply Analog Interface Circuit | |||
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3.6 Timing Requirements and Specifications in Master Mode
3.6.1 Recommended Input Timing Requirements for Master Mode, VDD = 5 V
MIN NOM MAX
tr(MCLK)
tf(MCLK)
Master clock rise time
Master clock fall time
Master clock duty cycle
40%
5
5
60%
tw(RESET)
tsu(DIN)
th(DIN)
RESET pulse duration
DIN setup time before SCLK low (see Figure 4â2)
DIN hold time after SCLK low (see Figure 4â2)
1 MCLK
25
20
UNIT
ns
ns
ns
ns
3.6.2
Operating Characteristics Over Recommended Range of Operating Free-Air
Temperature, VDD = 5 V (Unless Otherwise Noted) (see Note 23)
PARAMETER
MIN TYPâ MAX UNIT
tf(SCLK)
tr(SCLK)
Shift clock fall time (see Figure 4â2)
Shift clock rise time (see Figure 4â2)
Shift clock duty cycle
45%
13
18 ns
13
18 ns
55%
td(CH-FL)
Delay time from SCLK high to FSD low
(see Figures 4â2 and 4â4 and Note 24)
5
15 ns
td(CH-FH)
td(CH-DOUT)
Delay time from SCLK high to FS high (see Figure 4â2)
Delay time from SCLK high to DOUT valid
(see Figures 4â2 and 4â7)
5
20 ns
20 ns
td(CH-DOUTZ)
Delay time from SCLKâ to DOUT in high-impedance state
(see Figure 4â8)
20
ns
td(ML-EL)
td(ML-EH)
tf(EL)
tr(EH)
Delay time from MCLK low to EOC low (see Figure 4â9)
Delay time from MCLK low to EOC high (see Figure 4â9)
EOC fall time (see Figure 4â9)
EOC rise time (see Figure 4â9)
40
ns
40
ns
13
ns
13
ns
td(MH-CH)
Delay time from MCLK high to SCLK high
50 ns
td(MH-CL)
Delay time from MCLK high to SCLK low
50 ns
â All typical values are at VDD = 5 V and TA = 25°C.
NOTES: 23. All timing specifications are valid with CL = 20 pF.
24. FSD occurs 1/2 shift-clock cycle ahead of FS when the device is operating in the master mode.
3â8
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