TLC320AC01C_15 Datasheet, PDF (15/92 Pages) Texas Instruments – Single-Supply Analog Interface Circuit

Stand-Alone Mode
X
The operating mode under which the device generates and uses its own shift clock
and frame-sync signal. The device has no slave devices.
The X represents a don’t-care bit position within the control register format.
2.2 Reset and Power-Down Functions
2.2.1 Reset
The TLC320AC01 resets both the internal counters and registers, including the programmed registers, by
any of the following:
• Applying power to the device, causing a power-on reset (POR)
• Applying a low reset pulse to RESET
• Reading in the programmable software reset bit (DS01 in register 6)
PWR DWN resets the counters only and preserves the programmed register contents.
2.2.2 Conditions of Reset
The two internal reset signals used for the reset and synchronization functions are as follows:
1. Counter reset: This signal resets all flip-flops and latches that are not externally programmed with
the exception of those generating the reset pulse itself. In addition, this signal resets the software
power-down bit.
Counter reset = power-on reset + RESET + RESET bit + PWR DWN
2. Register reset: This signal resets all flip-flops and latches that are not reset by the counter reset
except those generating the reset pulse itself.
Register reset = power-on reset + RESET + RESET bit
Both reset signals are at least one master-clock period long and release on the falling edge of the master
clock.
2.2.3 Software and Hardware Power-Down
Given the definitions and conditions of RESET, the software-programmed power-down condition is cleared
by resetting the software bit (DS00 in register 6) to zero. It is also cleared by either cycling the power to the
device, bringing PWR DWN low, or bringing RESET low.
PWR DWN powers down the entire chip ( < 1 mA ). The software-programmable power-down bit only
powers down the analog section of the chip ( < 3 mA ), which allows a software power-up function. Cycling
PWR DWN high to low and back to high resets all flip-flops and latches that are not externally programmed,
thereby preserving the register contents.
When PWR DWN is not used, it should be tied high.
2.2.4 Register Default Values After POR, Software Reset, or RESET Is Applied
Register 1 – The A Register
The default value of the A-register data is decimal 18 as shown below.
DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
0
0
0
1
0
0
1
0
2–2