MSP430F6459-HIREL Datasheet, PDF (49/125 Pages) Texas Instruments – Mixed-Signal Microcontroller

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MSP430F6459-HIREL
SLASEC3A – AUGUST 2016 – REVISED AUGUST 2016
Table 5-39. Flash Memory
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN TYP MAX UNIT
DV_{CC(PGM/ERASE)}
I_PGM
I_ERASE
I_MERASE, I_BANK
Program and erase supply voltage
Average supply current from DVCC during program
Average supply current from DVCC during erase
Average supply current from DVCC during mass erase or bank
erase
t_CPT
Cumulative program time
Program and erase endurance
See ⁽¹⁾
1.8
3.6 V
3
5 mA
6
17 mA
6
17 mA
10³
10⁵
16 ms
cycles
t_Retention
t_Word
t_{Block, 0}
Data retention duration
Word or byte program time
Block program time for first byte or word
T_J = 25°C
100
See ⁽²⁾
64
See ⁽²⁾
49
t_{Block, 1–(N–1)}
Block program time for each additional byte or word, except for last
byte or word
See ⁽²⁾
37
t_{Block, N}
Block program time for last byte or word
See ⁽²⁾
55
t_{Seg Erase}
Erase time for segment, mass erase, and bank erase when
available
See ⁽²⁾
23
years
85 µs
65 µs
49 µs
73 µs
32 ms
f_MCLK,MRG
MCLK frequency in marginal read mode
(FCTL4.MRG0 = 1 or FCTL4.MRG1 = 1)
0
1 MHz
(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word write, individual byte write, and block write modes.
(2) These values are hardwired into the state machine of the flash controller.
5.14.4 Emulation and Debug
Table 5-40. JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN TYP
f_SBW
t_SBW,Low
t_{SBW, En}
t_SBW,Rst
f_TCK
Spy-Bi-Wire input frequency
Spy-Bi-Wire low clock pulse duration
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)⁽¹⁾
Spy-Bi-Wire return to normal operation time
TCK input frequency for 4-wire JTAG⁽²⁾
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V
3V
0
0.025
15
0
0
R_internal
Internal pulldown resistance on TEST
2.2 V, 3 V
45
60
MAX UNIT
20 MHz
15 µs
1 µs
100 µs
5
MHz
10
80 kΩ
(1) Tools that access the Spy-Bi-Wire interface must wait for the t_SBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
(2) f_TCK may be restricted to meet the timing requirements of the module selected.
Copyright © 2016, Texas Instruments Incorporated
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Specifications
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