MSP430F6459-HIREL Datasheet, PDF (39/125 Pages) Texas Instruments – Mixed-Signal Microcontroller

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MSP430F6459-HIREL
SLASEC3A – AUGUST 2016 – REVISED AUGUST 2016
Table 5-25. 12-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
f_ADC12CLK ADC conversion clock
TEST CONDITIONS
For specified performance of ADC12 linearity
parameters using an external reference voltage or
AV_CC as reference⁽¹⁾
For specified performance of ADC12 linearity
parameters using the internal reference⁽²⁾
V_CC
2.2 V, 3 V
MIN TYP MAX UNIT
0.45 4.8 5.0
0.45
2.4
4.0 ^MHz
For specified performance of ADC12 linearity
parameters using the internal reference⁽³⁾
0.45 2.4 2.7
f_ADC12OSC
Internal ADC12
oscillator ⁽⁴⁾
ADC12DIV = 0, f_ADC12CLK = f_ADC12OSC
2.2 V, 3 V
4.2 4.8 5.4 MHz
t_CONVERT Conversion time
REFON = 0, Internal oscillator,
ADC12OSC used for ADC conversion clock
External f_ADC12CLK from ACLK, MCLK or SMCLK,
ADC12SSEL ≠ 0
2.2 V, 3 V
2.4
See
(5)
3.1
µs
t_Sample
Sampling time
R_S = 400 Ω, R_I = 200 Ω, C_I = 20 pF,
τ = [R_S + R_I] × C_I ⁽⁶⁾
2.2 V, 3 V 1000
ns
(1) REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AV_CC as reference voltage: SREF2 = 0, SREF1 = 0,
SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock sources, the
specified performance of the ADC12 linearity is ensured with f_ADC12CLK maximum of 5.0 MHz.
(2) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1
(3) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured when
using the ADC12OSC divided by 2.
(4) The ADC12OSC is sourced directly from MODOSC inside the UCS.
(5) 13 × ADC12DIV × 1/f_ADC12CLK
(6) Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB:
t_Sample = ln(2ⁿ⁺¹) x (R_S + R_I) × C_I + 800 ns, where n = ADC resolution = 12, R_S = external source resistance
Table 5-26. 12-Bit ADC, Linearity Parameters Using an External Reference Voltage
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
E_I
Integral linearity error⁽¹⁾
E_D
Differential linearity error⁽¹⁾
E_O
Offset error⁽³⁾
E_G
Gain error⁽³⁾
E_T
Total unadjusted error
TEST CONDITIONS
1.4 V ≤ dVREF ≤ 1.6 V⁽²⁾
1.6 V < dVREF ⁽²⁾
See ⁽²⁾
dVREF ≤ 2.2 V⁽²⁾
dVREF > 2.2 V⁽²⁾
See ⁽²⁾
dVREF ≤ 2.2 V⁽²⁾
dVREF > 2.2 V⁽²⁾
V_CC
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
MIN TYP MAX UNIT
±2
LSB
±1.7
±1 LSB
±3 ±5.6
LSB
±1.5 ±3.5
±1 ±2.5 LSB
±3.5 ±7.1
LSB
±2
±5
(1) Parameters are derived using the histogram method.
(2) The external reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 0. dVREF = V_R+ – V_R–. V_R+ < AVCC. V_R– > AVSS.
Unless otherwise mentioned dVREF > 1.5 V. Impedance of the external reference voltage R < 100 Ω and two decoupling capacitors, 10
µF and 100 nF, should be connected to VREF to decouple the dynamic current. See also the MSP430F5xx and MSP430F6xx Family
User's Guide (SLAU208).
(3) Parameters are derived using a best fit curve.
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