MSP430F5529_17 Datasheet, PDF (49/128 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526
MSP430F5525, MSP430F5524, MSP430F5522, MSP430F5521
MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
SLAS590M – MARCH 2009 – REVISED NOVEMBER 2015
5.48 Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN TYP MAX UNIT
DV_{CC(PGM,ERASE)}
I_PGM
I_ERASE
I_MERASE, I_BANK
Program and erase supply voltage
Average supply current from DVCC during program⁽¹⁾
Average supply current from DVCC during erase⁽¹⁾
Average supply current from DVCC during mass erase or bank
erase ⁽¹⁾
t_CPT
Cumulative program time
Program and erase endurance
See ⁽²⁾
1.8
3.6 V
3
5 mA
6
11 mA
6
11 mA
10⁴
10⁵
16 ms
cycles
t_Retention
t_Word
t_{Block, 0}
Data retention duration
Word or byte program time
Block program time for first byte or word
T_J = 25°C
100
See ⁽³⁾
64
See ⁽³⁾
49
t_{Block, 1–(N–1)}
Block program time for each additional byte or word, except for last
byte or word
See ⁽³⁾
37
t_{Block, N}
Block program time for last byte or word
See ⁽³⁾
55
t_Erase
Erase time for segment, mass erase, and bank erase when
available.
See ⁽³⁾
23
years
85 µs
65 µs
49 µs
73 µs
32 ms
f_MCLK,MRG
MCLK frequency in marginal read mode
(FCTL4.MRG0 = 1 or FCTL4.MRG1 = 1)
0
1 MHz
(1) Default clock system frequency of MCLK = 1 MHz, ACLK = 32768 Hz, SMCLK = 1 MHz. No peripherals are enabled or active.
(2) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word- or byte-write and block-write modes.
(3) These values are hardwired into the state machine of the flash controller.
5.49 JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN TYP
f_SBW
t_SBW,Low
t_{SBW, En}
Spy-Bi-Wire input frequency
Spy-Bi-Wire low clock pulse duration
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
edge) ⁽¹⁾
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
0
0.025
t_SBW,Rst
f_TCK
Spy-Bi-Wire return to normal operation time
TCK input frequency, 4-wire JTAG⁽²⁾
15
2.2 V
0
3V
0
R_internal
Internal pulldown resistance on TEST
2.2 V, 3 V
45
60
MAX UNIT
20 MHz
15 µs
1 µs
100 µs
5
MHz
10
80 kΩ
(1) Tools that access the Spy-Bi-Wire interface must wait for the t_SBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
(2) f_TCK may be restricted to meet the timing requirements of the module selected.
Copyright © 2009–2015, Texas Instruments Incorporated
Specifications
49
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MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513