MSP430F5529_17 Datasheet, PDF (13/128 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526
MSP430F5525, MSP430F5524, MSP430F5522, MSP430F5521
MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
SLAS590M – MARCH 2009 – REVISED NOVEMBER 2015
Figure 4-6 shows the pinout for the MSP430F5528, MSP430F5526, and MSP430F5524 devices in the
YFF package.
TOP VIEW
BALL-SIDE VIEW
H8 H7 H6 H5 H4 H3 H2 H1
P2.7 P3.1 DVSS2 DVCC2 P4.1 P4.4 VSSU PU.0
G8 G7 G6 G5 G4 G3 G2 G1
P3.0 P3.2 P3.3 P3.4 P4.2 P4.5 PUR PU.1
F8
F7 F6
F5
F4
F3 F2 F1
P2.4 P2.5 P2.6 P4.0 P4.3 P4.6 VBUS VUSB
E8
E7 E6
E5
E4
E3 E2 E1
D
P2.1 P2.2 P2.3 P2.0 P4.7 TEST V18 P5.2
D8
P1.7
D7 D6 D5 D4
P1.6 P1.5 RST/NMI PJ.1
D3 D2 D1
PJ.0 AVSS2 P5.3
C8 C7 C6 C5 C4 C3 C2 C1
P1.3 P1.4 P1.2 P6.7 P6.3 P6.1 PJ.3 PJ.2
B8
B7 B6
B5
B4
B3 B2 B1
VCORE P1.0 P1.1 P5.1 P5.0 P6.5 P6.4 P6.0
A8
A7 A6
A5
A4
A3 A2 A1
DVSS1 DVCC1 P5.5 P5.4 AVSS1 AVCC1 P6.6 P6.2
H1 H2 H3 H4 H5 H6 H7 H8
PU.0 VSSU P4.4 P4.1 DVCC2 DVSS2 P3.1 P2.7
G1 G2 G3 G4 G5 G6 G7 G8
PU.1 PUR P4.5 P4.2 P3.4 P3.3 P3.2 P3.0
F1 F2 F3 F4 F5 F6 F7 F8
VUSB VBUS P4.6 P4.3 P4.0 P2.6 P2.5 P2.4
E1 E2 E3 E4 E5 E6 E7 E8
D
P5.2 V18 TEST P4.7 P2.0 P2.3 P2.2 P2.1
D1 D2 D3 D4 D5 D6 D7 D8
P5.3 AVSS2 PJ.0 PJ.1 RST/NMI P1.5 P1.6 P1.7
C1 C2 C3 C4 C5 C6 C7 C8
PJ.2 PJ.3 P6.1 P6.3 P6.7 P1.2 P1.4 P1.3
B1 B2 B3 B4 B5 B6 B7 B8
P6.0 P6.4 P6.5 P5.0 P5.1 P1.1 P1.0 VCORE
A1 A2 A3 A4 A5 A6 A7 A8
P6.2 P6.6 AVCC1 AVSS1 P5.4 P5.5 DVCC1 DVSS1
E
E
Figure 4-6. Pin Designation – MSP430F5528IYFF, MSP430F5526IYFF, MSP430F5524IYFF
Copyright © 2009–2015, Texas Instruments Incorporated
Terminal Configuration and Functions
13
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Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524
MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513