MSP430F5529_17 Datasheet, PDF (35/128 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526
MSP430F5525, MSP430F5524, MSP430F5522, MSP430F5521
MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
SLAS590M – MARCH 2009 – REVISED NOVEMBER 2015
5.29 USCI (UART Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
f_USCI
PARAMETER
USCI input clock frequency
CONDITIONS
Internal: SMCLK, ACLK,
External: UCLK,
Duty cycle = 50% ± 10%
V_CC
MIN MAX UNIT
f_SYSTEM MHz
f_BITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
1 MHz
5.30 USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
t_t
UART receive deglitch time⁽¹⁾
TEST CONDITIONS
V_CC
2.2 V
3V
MIN MAX UNIT
50
600
ns
50
600
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
5.31 USCI (SPI Master Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
f_USCI
PARAMETER
USCI input clock frequency
CONDITIONS
Internal: SMCLK, ACLK,
Duty cycle = 50% ± 10%
V_CC
MIN MAX UNIT
f_SYSTEM MHz
5.32 USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾
(see Figure 5-11 and Figure 5-12)
f_USCI
PARAMETER
USCI input clock frequency
TEST CONDITIONS
SMCLK, ACLK,
Duty cycle = 50% ± 10%
V_CC
MIN MAX UNIT
f_SYSTEM MHz
t_SU,MI
SOMI input data setup time
PMMCOREV = 0
PMMCOREV = 3
1.8 V
55
3.0 V
38
ns
2.4 V
30
3.0 V
25
t_HD,MI
SOMI input data hold time
PMMCOREV = 0
PMMCOREV = 3
1.8 V
0
3.0 V
0
ns
2.4 V
0
3.0 V
0
t_VALID,MO
SIMO output data valid time⁽²⁾
UCLK edge to SIMO valid,
C_L = 20 pF, PMMCOREV = 0
UCLK edge to SIMO valid,
C_L = 20 pF, PMMCOREV = 3
1.8 V
3.0 V
2.4 V
3.0 V
20
18
ns
16
15
t_HD,MO
SIMO output data hold time⁽³⁾
1.8 V
–10
C_L = 20 pF, PMMCOREV = 0
3.0 V
–8
ns
2.4 V
–10
C_L = 20 pF, PMMCOREV = 3
3.0 V
–8
(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI ≥ max(t_{VALID,MO(USCI)} + t_SU,SI(Slave), t_SU,MI(USCI) + t_{VALID,SO(Slave)}).
For the slave parameters t_SU,SI(Slave) and t_{VALID,SO(Slave)}, see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-11 and Figure 5-12.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-
11 and Figure 5-12.
Copyright © 2009–2015, Texas Instruments Incorporated
Specifications
35
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