LM3S5951 Datasheet, PDF (483/1261 Pages) Texas Instruments – Stellaris® LM3S5951 Microcontroller

Stellaris^® LM3S5951 Microcontroller
In addition to generating interrupts, an ADC and/or a μDMA trigger can be generated. The ADC
trigger is enabled by setting the TnOTE bit in GPTMCTL.The μDMA trigger is enabled by configuring
and enabling the appropriate μDMA channel. See “Channel Configuration” on page 363.
After an event has been captured, the timer does not stop counting. It continues to count until the
TnEN bit is cleared. When the timer reaches the timeout value, it is reloaded with the value from the
GPTMTnILR register.
Figure 10-4 on page 483 shows how input edge timing mode works. In the diagram, it is assumed
that the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture
rising edge events.
Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR
register, and is held there until another rising edge is detected (at which point the new count value
is loaded into the GPTMTnR register).
Figure 10-4. 16-Bit Input Edge-Time Mode Example
Count
0xFFFF
Z
GPTMTnR=X
GPTMTnR=Y GPTMTnR=Z
X
Y
Time
Input Signal
10.3.2.5
PWM Mode
Note: The prescaler is not available in 16-Bit PWM mode.
The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a
16-bit down-counter with a start value (and thus period) defined by the GPTMTnILR register. In this
mode, the PWM frequency and period are synchronous events and therefore guaranteed to be
glitch free. PWM mode is enabled with the GPTMTnMR register by setting the TnAMS bit to 0x1,
the TnCMR bit to 0x0, and the TnMR field to 0x1 or 0x2. Table 10-10 on page 483 shows the values
that are loaded into the timer registers when the timer is enabled.
Table 10-10. Counter Values When the Timer is Enabled in PWM Mode
Register
GPTMTnR
GPTMTnV
Count Down Mode
GPTMTnILR
GPTMTnILR
Count Up Mode
Not available
Not available
January 20, 2012
483
Texas Instruments-Production Data