LM3S5951 Datasheet, PDF (12/1261 Pages) Texas Instruments – Stellaris® LM3S5951 Microcontroller

Table of Contents
Figure 12-7. ADC Input Equivalency Diagram ......................................................................... 554
Figure 12-8. Internal Voltage Conversion Result ..................................................................... 555
Figure 12-9. External Voltage Conversion Result .................................................................... 556
Figure 12-10. Differential Sampling Range, V_{IN_ODD} = 1.5 V ...................................................... 557
Figure 12-11. Differential Sampling Range, V_{IN_ODD} = 0.75 V .................................................... 558
Figure 12-12. Differential Sampling Range, V_{IN_ODD} = 2.25 V .................................................... 558
Figure 12-13. Internal Temperature Sensor Characteristic ......................................................... 559
Figure 12-14. Low-Band Operation (CIC=0x0 and/or CTC=0x0) ................................................ 562
Figure 12-15. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ................................................. 563
Figure 12-16. High-Band Operation (CIC=0x3 and/or CTC=0x3) ................................................ 564
Figure 13-1. UART Module Block Diagram ............................................................................. 626
Figure 13-2. UART Character Frame ..................................................................................... 629
Figure 13-3. IrDA Data Modulation ......................................................................................... 631
Figure 13-4. LIN Message ..................................................................................................... 633
Figure 13-5. LIN Synchronization Field ................................................................................... 634
Figure 14-1. SSI Module Block Diagram ................................................................................. 690
Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 694
Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 694
Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 695
Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 695
Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 696
Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 697
Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 697
Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 698
Figure 14-10. MICROWIRE Frame Format (Single Frame) ........................................................ 699
Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 700
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 700
Figure 15-1. I²C Block Diagram ............................................................................................. 732
Figure 15-2. I²C Bus Configuration ........................................................................................ 733
Figure 15-3. START and STOP Conditions ............................................................................. 734
Figure 15-4. Complete Data Transfer with a 7-Bit Address ....................................................... 734
Figure 15-5. R/S Bit in First Byte ............................................................................................ 735
Figure 15-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 735
Figure 15-7. Master Single TRANSMIT .................................................................................. 739
Figure 15-8. Master Single RECEIVE ..................................................................................... 740
Figure 15-9. Master TRANSMIT with Repeated START ........................................................... 741
Figure 15-10. Master RECEIVE with Repeated START ............................................................. 742
Figure 15-11. Master RECEIVE with Repeated START after TRANSMIT with Repeated
START .............................................................................................................. 743
Figure 15-12. Master TRANSMIT with Repeated START after RECEIVE with Repeated
START .............................................................................................................. 744
Figure 15-13. Slave Command Sequence ................................................................................ 745
Figure 16-1. I²S Block Diagram ............................................................................................. 770
Figure 16-2. I²S Data Transfer ............................................................................................... 773
Figure 16-3. Left-Justified Data Transfer ................................................................................ 773
Figure 16-4. Right-Justified Data Transfer .............................................................................. 773
Figure 17-1. CAN Controller Block Diagram ............................................................................ 807
Figure 17-2. CAN Data/Remote Frame .................................................................................. 809
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January 20, 2012
Texas Instruments-Production Data