OMAP3530ECUS Datasheet, PDF (47/264 Pages) Texas Instruments – OMAP3530/25 Applications Processor: OMAP 3 Architecture

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OMAP3530/25 Applications Processor
SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009
Table 2-1. Ball Characteristics (CBB Pkg.) (continued)
BALL
BALL TOP PIN NAME MODE [4] TYPE [5]
BOTTOM [1] [2]
[3]
AH1, AH2, A2, A12,
FeedThrough -
-
AH10, AH11, A22, A23, Pins⁽⁵⁾
AH13, AH15, AA1, AA2,
AH16, AH27, AA22, AA23,
AH28, AG1, AB1, AB11,
AG10, AG11, AB13, AB23,
AG13, AG15, AB8, AB9,
AG28, AF1, AC1, AC11,
AF2, AF27, AC13, AC14,
AF28, AE28, AC2, AC22,
AA1, AA2, AC23, AC8,
N1, N2, M1, AC9, B12,
M2, M26, B23, H22,
J27, J28, H23, K1, K2,
B15, B28, K22, L1, L2,
A2, A15,
U1, U2, Y23
A27, A28
A1, B1, G1, A1, AB2, No Connect -
-
U4
AB22, B1,
B2, B22
BALL
RESET
STATE [6]
-
BALL
RESET REL. POWER [9] HYS [10]
RESET REL. MODE [8]
STATE [7]
-
-
-
-
BUFFER PULLUP
STRENG TH /DOWN
(mA) [11] TYPE [12]
-
-
(5) These signals are feed-through balls. For more information, see Section 2.5.10.
IO CELL [13]
-
Table 2-2. Ball Characteristics (CBC Pkg.)⁽¹⁾
BALL
BALL TOP PIN NAME
BOTTOM [1]
[2]
[3]
MODE [4]
AE16
NA
cam_d0
0
AE15
gpio_99
4
safe_mode
7
NA
cam_d1
0
AD17
gpio_100
4
safe_mode
7
NA
gpio_112
4
AE18
safe_mode
7
NA
gpio_114
4
AD16
safe_mode
7
NA
gpio_113
4
AE17
safe_mode
7
NA
gpio_115
4
safe_mode
7
NA
G20
sdrc_a0
0
NA
K20
sdrc_a1
0
NA
J20
sdrc_a2
0
NA
J21
sdrc_a3
0
NA
U21
sdrc_a4
0
NA
R20
sdrc_a5
0
NA
M21
sdrc_a6
0
NA
M20
sdrc_a7
0
NA
N20
sdrc_a8
0
NA
K21
sdrc_a9
0
NA
Y16
sdrc_a10
0
NA
N21
sdrc_a11
0
NA
R21
sdrc_a12
0
NA
AA15
sdrc_a13
0
NA
Y12
sdrc_a14
0
TYPE [5]
I
I
-
I
I
-
I
-
I
-
I
-
I
-
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
RESET REL.
MODE [8]
POWER [9]
L
L
7
vdds
HYS [10]
Yes
BUFFER PULLUP
STRENG TH /DOWN IO CELL [13]
(mA) [11] TYPE [12]
4
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
4
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
4
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
4
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
4
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
4
PU100/
LVCMOS
PD100
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
(1) NA in this table stands for Not Applicable.
(2) The drive strength is programmable vs the capacity load: load range = [2 pF to 6 pF] per default or [6 pF to 12 pF] according to the
selected mode.
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