OMAP3530ECUS Datasheet, PDF (35/264 Pages) Texas Instruments – OMAP3530/25 Applications Processor: OMAP 3 Architecture

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OMAP3530/25 Applications Processor
SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009
Table 2-1. Ball Characteristics (CBB Pkg.) (continued)
BALL
BALL TOP PIN NAME MODE [4] TYPE [5]
BOTTOM [1] [2]
[3]
gpio_126 4
IO
safe_mode 7
AG19
NA
gpio_112 4
I
safe_mode 7
AH19
NA
gpio_113 4
I
safe_mode 7
AG18
NA
gpio_114 4
I
safe_mode 7
AH18
NA
gpio_115 4
I
safe_mode 7
P21
NA
mcbsp2_fsx 0
IO
gpio_116 4
IO
safe_mode 7
N21
NA
mcbsp2_ 0
IO
clkx
gpio_117 4
IO
safe_mode 7
R21
NA
mcbsp2_dr 0
I
gpio_118 4
IO
safe_mode 7
M21
NA
mcbsp2_dx 0
IO
gpio_119 4
IO
safe_mode 7
N28
NA
mmc1_clk 0
O
gpio_120 4
IO
safe_mode 7
M27
NA
mmc1_cmd 0
IO
gpio_121 4
IO
safe_mode 7
N27
NA
mmc1_dat0 0
IO
gpio_122 4
IO
safe_mode 7
N26
NA
mmc1_dat1 0
IO
gpio_123 4
IO
safe_mode 7
N25
NA
mmc1_dat2 0
IO
gpio_124 4
IO
safe_mode 7
P28
NA
mmc1_dat3 0
IO
gpio_125 4
IO
safe_mode 7
P27
NA
mmc1_dat4 0
IO
gpio_126 4
IO
safe_mode 7
P26
NA
mmc1_dat5 0
IO
gpio_127 4
IO
safe_mode 7
R27
NA
mmc1_dat6 0
IO
gpio_128 4
IO
safe_mode 7
R25
NA
mmc1_dat7 0
IO
BALL
RESET
STATE [6]
BALL
RESET REL. POWER [9] HYS [10]
RESET REL. MODE [8]
STATE [7]
L
L
7
vdds
Yes
L
L
7
vdds
Yes
L
L
7
vdds
Yes
L
L
7
vdds
Yes
L
L
7
vdds
Yes
L
L
7
vdds
Yes
L
L
7
vdds
Yes
L
L
7
vdds
Yes
L
L
7
vdds_mmc1 Yes
L
L
7
vdds_mmc1 Yes
L
L
7
vdds_mmc1 Yes
L
L
7
vdds_mmc1 Yes
L
L
7
vdds_mmc1 Yes
L
L
7
vdds_mmc1 Yes
L
L
7
vdds_mmc1a No
L
L
7
vdds_mmc1a No
L
L
7
vdds_mmc1a No
L
L
7
vdds_mmc1a No
BUFFER PULLUP
STRENG TH /DOWN
(mA) [11] TYPE [12]
NA
PU/PD
NA
PU/PD
NA
PU/PD
NA
PU/PD
4 ⁽³⁾
PU/ PD
4 ⁽³⁾
PU/ PD
4 ⁽³⁾
PU/ PD
4 ⁽³⁾
PU/ PD
8
PU/ PD⁽⁴⁾
8
PU/ PD⁽⁴⁾
8
PU/ PD⁽⁴⁾
8
PU/ PD⁽⁴⁾
8
PU/ PD ⁽⁴⁾
8
PU/ PD⁽⁴⁾
8
PD ⁽⁴⁾
8
PD ⁽⁴⁾
8
PD ⁽⁴⁾
8
PD ⁽⁴⁾
IO CELL [13]
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
(3) The buffer strength of this IO cell is programmable (2, 4, 6, or 8 mA) according to the selected mode; the default value is described in
the above table.
(4) The PU nominal drive strength of this IO cell is equal to 25 uA @ 1.8V and 41.6 uA @ 3.0V. The PD nominal drive strength of this IO
cell is equal to 1 mA @ 1.8V and 1.66 mA @ 3.0V.
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TERMINAL DESCRIPTION
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