OMAP3530ECUS Datasheet, PDF (210/264 Pages) Texas Instruments – OMAP3530/25 Applications Processor: OMAP 3 Architecture

OMAP3530/25 Applications Processor
SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009
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6.6.2 Multichannel Serial Port Interface (McSPI) Timing
The multichannel SPI is a master/slave synchronous serial bus. The McSPI1 module supports up to four
peripherals and the others (McSPI2, McSPI3, and McSPI4) support up to two peripherals. The following
timings are applicable to the different configurations of McSPI in master/slave mode for any McSPI and
any channel (n).
6.6.2.1 McSPI in Slave Mode
Table 6-71 and Table 6-72 assume testing over the recommended operating conditions (see Figure 6-41).
Table 6-71. McSPI Interface Timing Requirements – Slave Mode⁽¹⁾⁽²⁾
NO.
1/SS 1/t_c(CLK)
0
SS1
SS2
t_j(CLK)
t_w(CLK)
t_{su(SIMOV-CLKAE)}
SS3 t_{h(SIMOV-CLKAE)}
SS4 t_{su(CS0V-CLKFE)}
SS5 t_{h(CS0I-CLKLE)}
PARAMETER
Frequency, mcspix_clk
1.15 V
MIN
MAX
24
1.0 V
MIN
MAX
12
Cycle jitter⁽³⁾, mcspix_clk
Pulse duration, mcspix_clk high or low
Setup time, mcspix_simo valid before mcspix_clk
active edge
Hold time, mcspix_simo valid after mcspix_clk active
edge
Setup time, mcspix_cs0 valid before mcspix_clk first
edge
Hold time, mcspix_cs0 invalid after mcspix_clk last
edge
-200
200
0.45*P⁽⁴⁾ 0.55*P⁽⁴⁾
4.2
4.6
13.8
13.8
-200
0.45*P ⁽⁴⁾
9.5
9.9
28.6
28.6
200
0.55*P ⁽⁴⁾
(1) The input timing requirements are given by considering a rise time and a fall time of 4 ns.
(2) In mcspix, x is equal to 1, 2, 3, or 4.
(3) Maximum cycle jitter supported by mcspix_clk input clock.
(4) P = mcspix_clk clock period
UNIT
MHz
ps
ns
ns
ns
ns
ns
Table 6-72. McSPI Interface Switching Requirements^(1)(2)(3)(4)
NO.
PARAMETER
SS6 t_{d(CLKAE-SOMIV)}
SS7 t_{d(CS0AE-SOMIV)}
Delay time, mcspix_clk active edge to mcspix_somi
shifted
Delay time, mcspix_cs0 active edge to Modes 0 and 2
mcspix_somi shifted
1.15 V
MIN
MAX
1.8
15.9
15.9
1.0 V
MIN
MAX
3.2
31.7
31.7
UNIT
ns
ns
(1) The capacitive load is equivalent to 20 pF.
(2) In mcspix, x is equal to 1, 2, 3, or 4.
(3) The polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all
software configurable.
(4) This timing applies to all configurations regardless of mcspix_clk polarity and which clock edges are used to drive output data and
capture input data.
210 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS
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