OMAP3530ECUS Datasheet, PDF (226/264 Pages) Texas Instruments – OMAP3530/25 Applications Processor: OMAP 3 Architecture

OMAP3530/25 Applications Processor
SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009
www.ti.com
Table 6-105. High-Speed USB Timing Requirements – 8-bit TLL Master Mode (continued)
NO.
PARAMETER
HSU5 t_{h(CLKH-DATIV)}
Hold time, hsusbx_tll_data[3:0] valid after hsusbx_tll_clk rising edge
1.15 V
MIN
MAX
–0.8
UNIT
ns
Table 6-106. High-Speed USB Switching Characteristics – 8-bit TLL Master Mode⁽¹⁾
NO.
PARAMETER
HSU0
f_p(CLK)
t_j(CLK)
hsusbx_tll_clk clock frequency
Jitter standard deviation⁽²⁾, hsusbx_tll_clk
HSU1 t_j(CLK)
Duty cycle, hsusbx_tll_clk pulse duration (low and high)
HSU6 t_d(CLKL-DIRV) Delay time, hsusbx_tll_clk high to output hsusbx_tll_dir valid
t_{d(CLKL-DIRIV)} Delay time, hsusbx_tll_clk high to output hsusbx_tll_dir invalid
t_d(CLKL-NXTV) Delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt valid
t_{d(CLKL-NXTIV)} Delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt invalid
HSU7 t_d(CLKL-DV)
Delay time, hsusbx_tll_clk high to output hsusbx_tll_data[3:0] valid
HSU8 t_d(CLKL-DIV)
Delay time, hsusbx_tll_clk high to output hsusbx_tll_data[3:0] invalid
t_R(do)
Rise time, output signals
t_F(do)
Fall time, output signals
(1) In hsusbx, x is equal to 1, 2, or 3.
(2) The jitter probability density can be approximated by a Gaussian function.
1.15 V
MIN
MAX
60
200
47.6%
52.4%
9
0
9
0
4
0
2
2
UNIT
MHz
ps
ns
ns
ns
ns
ns
ns
ns
ns
hsusbx_tll_clk
hsusbx_tll_stp
hsusbx_tll_dir_&_nxt
hsusbx_tll_data[3:0]
HSU0
HSU1
HSU1
HSU2
HSU3
HSU6
HSU4
Data_IN
HSU5
HSU4
Data_IN_(n+1)
HSU5
Data_IN_(n+2)
In hsusbx, x is equal to 1, 2, or 3.
HSU6
HSU7
Data_OUT
HSU8
HSU7
Data_OUT_(n+1)
030-089
Figure 6-52. High-Speed USB – 8-bit TLL Master Mode
226 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS
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