TLC320AD90 Datasheet, PDF (43/51 Pages) Texas Instruments – Stereo Audio Codec

3.4.3 Data Setup and Hold Timing
PARAMETER
tsu1 Setup time, SDATA_IN, SDATA_OUT, SYNC valid to BIT_CLK↓
th1 Hold time, BIT_CLK↓ to SDATA_IN, SDATA_OUT, SYNC invalid
MIN TYP MAX UNIT
15
ns
5
ns
3.4.4 Signal Rise and Fall Timing
PARAMETER
tr(CLK)
tf(CLK)
tr(DIN)
tf(DIN)
tr(DOUT)
tf(DOUT)
tr(SYNC)
tf(SYNC)
Rise time, BIT_CLK
Fall time, BIT_CLK
Rise time, SDATA_IN
Fall time, SDATA_IN
Rise time, SDATA_OUT
Fall time, SDATA_OUT
Rise time, SYNC
Fall time, SYNC
MIN TYP MAX UNIT
2
6 ns
2
6 ns
2
6 ns
2
6 ns
2
6 ns
2
6 ns
2
6 ns
2
6 ns
3.4.5 Warm/Cold Reset Timing, T_A = 25°C, AV_DD = DV_DD = 5 V dc,
AV_SS = DV_SS = 0 V, 50-pF External Load
PARAMETER
MIN TYP MAX UNIT
twL(RST)
td(RST_CLK)
Pulse width, RESET low
Delay time, RESET↑ to BIT_CLK↑
1
ms
162.8
ns
PARAMETER
twH(SYNC)
Pulse width, SYNC high
td(SYNC_CLK) Delay time, SYNC↓ to BIT_CLK↑
MIN
1
162.8
TYP MAX UNIT
1.3
ms
ns
3.4.6 ATE Test Mode Timing, T_A = 25°C, AV_DD = DV_DD = 5 V dc,
AV_SS = DV_SS = 0 V, 50-pF External Load
PARAMETER
MIN TYP MAX UNIT
tsu3
Setup time, SDATA_OUT↑, SYNC to RESET↑ (see Notes 17
and 18)
15
ns
td(off)
Delay time, RESET↑ to SDATA_IN, BIT_CLK Hi-Z (see
Notes 17 and 18)
25 ns
NOTES: 17. All AC-Link signals are normally low though RESET↑. SDATA_OUT should be high prior to RESET↑ which
causes the TLC320AD90C AC-Link outputs to go high impedance which is suitable for ATE in circuit
testing.
18. The Texas Instruments internal test mode is entered by bringing SYNC high prior to RESET↑. This mode
has no effect on the TLC320AD90C AC-Link output signal levels.
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