TLC320AD90 Datasheet, PDF (16/51 Pages) Texas Instruments – Stereo Audio Codec

The AC-Link signal definitions are listed in Table 2–1.
Table 2–1. AC-Link Signal Definitions
SIGNAL
SYNC
BIT_CLK
SOURCE
DESCRIPTION
Controller
Marks the beginning of each frame. Sourced by the controller. Occurs at a fixed
rate of 48 kHz unless in power-down mode. Synchronous to BIT_CLK. Width of
16 bits. Defines the TAG phase.
Codec
Sourced by TLC320AD90C. Fixed rate of 12.288 MHz. Data is transmitted on
every rising edge. Data is captured on every falling edge.
SDATA_OUT
Controller
Serial bit stream sent from the controller to the codec. Data and control are
transmitted by the controller.
SDATA_IN
Codec
Serial bit stream sent from the codec to the controller. Data and control are
transmitted by the TLC320AD90C.
RESET
Controller
Reset signal used to bring the TLC320AD90C out of power-down mode. Defines
the cold TLC320AD90C reset.
2.2.2 Protocol
The TLC320AD90C protocol includes the following:
• The AC-Link is a TDM serial interface consisting of 256 bits/frame
• Each frame is divided into two sections: A TAG phase of 16 bits, and a DATA phase of 240 bits
• The DATA phase is divided into 12 time slots with each time slot consisting of 20 bits
• Data is bidirectional with SDATA_OUT transmitted by the controller, and SDATA_IN transmitted
by the codec
BIT_CLK
SYNC
SDATA_OUT
SDATA_IN
Valid ^{Slot Slot}
Slot 0 0 0 19
0 19
0
12
12
Cdc Slot Slot
Slot 0 0 0 19
0 19
0
Rdy 1 2
12
19
0
19
0
TAG Phase
Slot 1
Slot 2
Slot 12
Figure 2–3. AC-Link Protocol
2.2.2.1 Zero-Padding
The TLC320AD90C uses zero-padding which is defined as the following:
• Reserved time-slots are filled with zeroes
• Unused bits within a time-slot must be filled with zeroes (e.g., 16-bit converter in a 20-bit time
slot). This operation must be performed by the source (i.e., the controller for SDATA_OUT, the
TLC320AD90C for SDATA_IN).
• Time slots tagged as invalid must be filled with zeroes
2–3