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TLC320AD90 Datasheet, PDF (41/51 Pages) Texas Instruments – Stereo Audio Codec
3.3.4.5 ADC Decimation Filter, TA = 25°C, AVDD = DVDD = 5 V ± 5%
PARAMETER
TEST CONDITIONS
MIN TYP
Pass band
20
Pass band ripple
see Note 15
Transition band
19.2
Stop band
28.8
Stop band attenuation (28.8 kHz to 3 MHz)
74
Group delay
NOTE 15: Exceeds the AC‘97 specification
" 3.3.4.6 DAC Interpolation Filter, TA = 25°C, AVDD = DVDD = 5 V 5%
PARAMETER
TEST CONDITIONS
MIN TYP
Pass band
20
Pass band ripple
see Note 15
Transition band
19.2
Stop band
28.8
Stop band attenuation
(28.8 kHz to 3 MHz)
74
Group delay
NOTE 15: Exceeds the AC‘97 specification
MAX
19.2
±0.1
28.8
0.6
UNIT
kHz
dB
kHz
kHz
dB
ms
MAX
"19.2
0.1
28.8
UNIT
kHz
dB
kHz
kHz
dB
0.6 ms
3.4 Timing Requirements
3.4.1 AC-Link Low-Power Mode Timing, TA = 25°C, AVDD = DVDD = 5 V dc,
AVSS = DVSS = 0 V, 50-pF External Load
PARAMETER
MIN TYP MAX UNIT
td1
Delay time, SDATA_IN↓ to BIT_CLK↓
1
ms
3.4.2 AC-Link Timing, TA = 25°C, AVDD = DVDD = 5 V dc, AVSS = DVSS = 0 V,
50-pF External Load
3.4.2.1 Clock Timing
PARAMETER
MIN TYP MAX UNIT
Frequency, BIT_CLK
tcyc(BIT_CLK) Cycle time, BIT_CLK
Jitter, BIT_CLK
twH(CLK)
twL(CLK)
Pulse width, BIT_CLK high (see Note 16)
Pulse width, BIT_CLK low (see Note 16)
Frequency, SYNC
12.288
81.4
750
32.56 40.7 48.84
32.56 40.7 48.84
48.0
MHz
ns
ps
ns
ns
kHz
tcyc(SYNC)
twH(SYNC)
twL(SYNC)
Cycle time, SYNC
Pulse width, SYNC high
Pulse width, SYNC low
20.8
ms
1.3
ms
19.5
ms
3–6