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TLC320AD90 Datasheet, PDF (29/51 Pages) Texas Instruments – Stereo Audio Codec
Table 2–14. Power-Down Control/Status Register Bits D8–D13 Definitions
BIT
FUNCTION (SEE NOTE 1)
PR0 PCM in ADCs and input mux power down
PR1 PCM out DACs power down
PR2 Analog mixer power down (Vref on)
PR3 Analog mixer power down (Vref off)
PR4 Digital interface (AC-Link) power down (external clock off)
PR5 Internal clock disabled
NOTE 1: PR6 and PR7 are specified in the AC‘97 specification, but are
not implemented in TLC320AD90C. These bits are read back
as zeroes.
2.3.9 Reserved Registers (Index 28h – 59h)
These registers are reserved. Write operations should not be performed to these registers.
2.3.10 Vendor Reserved Registers (Index 5Ah – 7Ah)
The Vendor Reserved registers are reserved for future use and are vendor specific. The TLC320AD90C
register positions are allocated in the architecture but all bits are permanently set to zero.
A write operation to any of the Vendor Reserved registers has no effect. A read operation of any of these
registers, except for index 5Ah, produces all zero values.
2.3.11 Vendor ID Registers (Index 7Ch – 7Eh)
The Vendor ID registers are for specific vendor identification, if so desired. The ID method is the Microsoft
Plug and Play™ vendor ID code with F7 – F0 containing the first character of that ID, S7 – S0 containing
the second ID character, and T7 – T0 containing the third ID character. These three characters are ASCII
encoded. The REV7 – REV0 field is for the vendor revision number.
Register 7Ch is hard coded with 5458h and register 7Eh is hard coded with 4E20h. Only these values are
read from these registers.
Plug and Play is a trademark of Microsoft Corporation.
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