SM320C6457-HIREL Datasheet, PDF (42/209 Pages) Texas Instruments – SM320C6457-HIREL Communications Infrastructure Digital Signal Processor

SM320C6457-HIREL
SPRS948 – JULY 2016
www.ti.com
Figure 4-6 shows a general transfer between the DSP and an external device. The figure also shows
board route delays and how they are perceived by the DSP and the external device
AECLKOUT
(Output from DSP)
AECLKOUT
(Input to External Device)
Control Signals ^(A)
(Output from DSP)
Control Signals
(Input to External Device)
Data Signals ^(B)
(Output from External Device)
Data Signals ^(B)
(Input to DSP)
1
2
3
4
5
6
7
8
9
10
11
Figure 4-6. Board-Level Input/Output Timings
(A) Control signals include data for writes.
(B) Data signals are generated during reads from an external device.
4.6.2 Power Supply Sequencing
The following sections describe the proper power-supply sequencing and timing needed to properly power
on the C6457 DSP. This section also describes proper power-supply decoupling methods.
TI recommends the power-supply sequence shown in Figure 4-7 and described in Table 4-3. The figure
shows that the 1.8-V I/O supply should be ramped first. This is followed by the scaled core supply and the
fixed 1.1-V supplies which must ramp within 5 ms of each other. The 3.3-V I/O supply should ramp up last.
Some TI power supply devices include features that facilitate power sequencing; for example, Auto-Track
or Slow-Start/Enable features. For more information, visit www.ti.com/dsppower. See the TMS320TCI6468
and TMS329C6457 DSPs Hardware Design Guide (SPRAAV7) for further details on proper power-supply
sequencing.
DV_DD18
V_REFSSTL (DDR2)
1
CV_DD11
DV_DD11
DV_DD33
POR
2
3
42
Specifications
Figure 4-7. Power Supply Sequence
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