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| SM320C6457-HIREL Datasheet, PDF (164/209 Pages) Texas Instruments – SM320C6457-HIREL Communications Infrastructure Digital Signal Processor | |||
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SM320C6457-HIREL
SPRS948 â JULY 2016
www.ti.com
4.8.19.3 IEEE 1149.1 JTAG
The JTAG interface is used to support boundary scan and emulation of the device. The boundary scan
supported allows for an asynchronous TRST and only the 5 baseline JTAG signals (e.g., no EMU[1:0])
required for boundary scan. Most interfaces on the device follow the Boundary Scan Test Specification
(IEEE1149.1), while all of the SerDes (SRIO and SGMII) support the AC-coupled net test defined in AC-
Coupled Net Test Specification (IEEE1149.6).
It is expected that all compliant devices are connected through the same JTAG interface, in daisy-chain
fashion, in accordance with the specification. The JTAG interface uses 1.8-V LVCMOS buffers, compliant
with the Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit
Specification (EAI/JESD8-5).
4.8.19.3.1 IEEE 1149.1 JTAG Compatibility Statement
For maximum reliability, the C6457 DSP includes an internal pulldown (IPD) on the TRST pin to ensure
that TRST will always be asserted upon power up and the DSP's internal emulation logic will always be
properly initialized when this pin is not routed out. JTAG controllers from Texas Instruments actively drive
TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of
an external pullup resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the
DSP after powerup and externally drive TRST high before attempting any emulation or boundary scan
operations.
4.8.19.3.2 JTAG Electrical Data/Timing
Table 4-101. JTAG Test Port Timing Requirements
(see Figure 4-68)
NO.
MIN
1 tc(TCK)
Cycle time, TCK
10
3 tsu(TDIV-TCKH)
Setup time, TDI/TMS/TRST valid before TCK high
2
4 th(TCKH-TDIV)
Hold time, TDI/TMS/TRST valid after TCK high
5
MAX UNIT
20 ns
ns
ns
Table 4-102. JTAG Test Port Switching Characteristics(1)
(see Figure 4-68)
NO. PARAMETER
MIN
MAX UNIT
2 td(TCKL-TDOV)
Delay time, TCK low to TDO valid
0.25 x tc(TCK) ns
(1) Over recommended operating conditions.
TCK
TDO
TDI/TMS/TRST
1
2
2
4
3
Figure 4-68. JTAG Test-Port Timing
164 Specifications
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