SM320C6457-HIREL Datasheet, PDF (4/209 Pages) Texas Instruments – SM320C6457-HIREL Communications Infrastructure Digital Signal Processor

SM320C6457-HIREL
SPRS948 – JULY 2016
1.5 Functional Block Diagram
Figure 1-1 Shows the functional block diagram of the SM320C6457-HIREL device.
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32
DDR2 SDRAM
64
I/O Devices
DDR2
Mem Ctlr
PLL2
EMIFA
TCP2_A
TCP2_B
VCP2
McBSP0
McBSP1
Serial Rapid
I/O
HPI (32/16)
UTOPIA
EMAC
10/100/1000
SGMII
MDIO
16
GPIO16
I2C
Timer1^(A)
HI
LO
Timer0^(A)
HI
LO
C6457
L1P SRAM/Cache Direct-Mapped
32K Bytes
L1P Memory Controller (Memory Protect/Bandwidth Mgmt)
L2
Cache
Memory
2048K
Bytes
C64x+ DSP Core
Instruction Fetch
Control Registers
16-/32-bit
Instruction Dispatch
Instruction
M
Decode
e
g
Data Path A
a
m
A Register File
o
A31−A16
d
A15−A0
u
l
e
.L1
.S1
.M1
xx
.D1
xx
SPLOOP Buffer
In-Circuit Emulation
Data Path B
B Register File
B31−B16
B15−B0
.D2
.M2
xx
.S2
.L2
xx
L1D Memory Controller (Memory Protect/Bandwidth Mgmt)
L1D SRAM/Cache
2-Way
Set-Associative
32K Bytes Total
EDMA 3.0
L3 ROM
Secondary
Switched Central
Resource
PLL1 and
PLL1
Controller
Device
Configuration
Logic
Boot Configuration
Figure 1-1. Functional Block Diagram
(A) Each of the TIMER peripherals (TIMER1 and TIMER0) is configurable as either one 64-bit general-purpose timer or two 32-bit general-
purpose timers or a watchdog timer.
4
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