SM320C6457-HIREL Datasheet, PDF (155/209 Pages) Texas Instruments – SM320C6457-HIREL Communications Infrastructure Digital Signal Processor

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SM320C6457-HIREL
SPRS948 – JULY 2016
HEX ADDRESS RANGE
02D0 0528
02D0 052C
02D0 0530
02D0 0534
02D0 0538
02D0 053C
02D0 0540 - 02D0 057C
02D0 0580
02D0 0584
02D0 0588
02D0 058C
02D0 0590
02D0 0594
02D0 0598
02D0 059C
02D0 05A0
02D0 05A4
02D0 05A8
02D0 05AC
02D0 05B0
02D0 05B4
02D0 05B8
02D0 05BC
02D0 05D0 - 02D0 05FC
02D0 0600
02D0 0604
02D0 0608
02D0 060C
02D0 0610
02D0 0614
02D0 0618
02D0 061C
02D0 0620
02D0 0624
02D0 0628
02D0 062C
02D0 0630
02D0 0634
02D0 0638
02D0 063C
02D0 0640 - 02D0 067C
02D0 0680
02D0 0684
02D0 0688
02D0 068C
02D0 0690
02D0 0694
Table 4-96. RapidIO Control Registers (continued)
ACRONYM
QUEUE10_TXDMA_HDP
QUEUE11_TXDMA_HDP
QUEUE12_TXDMA_HDP
QUEUE13_TXDMA_HDP
QUEUE14_TXDMA_HDP
QUEUE15_TXDMA_HDP
-
QUEUE0_TXDMA_CP
QUEUE1_TXDMA_CP
QUEUE2_TXDMA_CP
QUEUE3_TXDMA_CP
QUEUE4_TXDMA_CP
QUEUE5_TXDMA_CP
QUEUE6_TXDMA_CP
QUEUE7_TXDMA_CP
QUEUE8_TXDMA_CP
QUEUE9_TXDMA_CP
QUEUE10_TXDMA_CP
QUEUE11_TXDMA_CP
QUEUE12_TXDMA_CP
QUEUE13_TXDMA_CP
QUEUE14_TXDMA_CP
QUEUE15_TXDMA_CP
-
QUEUE0_RXDMA_HDP
QUEUE1_RXDMA_HDP
QUEUE2_RXDMA_HDP
QUEUE3_RXDMA_HDP
QUEUE4_RXDMA_HDP
QUEUE5_RXDMA_HDP
QUEUE6_RXDMA_HDP
QUEUE7_RXDMA_HDP
QUEUE8_RXDMA_HDP
QUEUE9_RXDMA_HDP
QUEUE10_RXDMA_HDP
QUEUE11_RXDMA_HDP
QUEUE12_RXDMA_HDP
QUEUE13_RXDMA_HDP
QUEUE14_RXDMA_HDP
QUEUE15_RXDMA_HDP
-
QUEUE0_RXDMA_CP
QUEUE1_RXDMA_CP
QUEUE2_RXDMA_CP
QUEUE3_RXDMA_CP
QUEUE4_RXDMA_CP
QUEUE5_RXDMA_CP
REGISTER NAME
Queue Transmit DMA Head Descriptor Pointer Register 10
Queue Transmit DMA Head Descriptor Pointer Register 11
Queue Transmit DMA Head Descriptor Pointer Register 12
Queue Transmit DMA Head Descriptor Pointer Register 13
Queue Transmit DMA Head Descriptor Pointer Register 14
Queue Transmit DMA Head Descriptor Pointer Register 15
Reserved
Queue Transmit DMA Completion Pointer Register 0
Queue Transmit DMA Completion Pointer Register 1
Queue Transmit DMA Completion Pointer Register 2
Queue Transmit DMA Completion Pointer Register 3
Queue Transmit DMA Completion Pointer Register 4
Queue Transmit DMA Completion Pointer Register 5
Queue Transmit DMA Completion Pointer Register 6
Queue Transmit DMA Completion Pointer Register 7
Queue Transmit DMA Completion Pointer Register 8
Queue Transmit DMA Completion Pointer Register 9
Queue Transmit DMA Completion Pointer Register 10
Queue Transmit DMA Completion Pointer Register 11
Queue Transmit DMA Completion Pointer Register 12
Queue Transmit DMA Completion Pointer Register 13
Queue Transmit DMA Completion Pointer Register 14
Queue Transmit DMA Completion Pointer Register 15
Reserved
Queue Receive DMA Head Descriptor Pointer Register 0
Queue Receive DMA Head Descriptor Pointer Register 1
Queue Receive DMA Head Descriptor Pointer Register 2
Queue Receive DMA Head Descriptor Pointer Register 3
Queue Receive DMA Head Descriptor Pointer Register 4
Queue Receive DMA Head Descriptor Pointer Register 5
Queue Receive DMA Head Descriptor Pointer Register 6
Queue Receive DMA Head Descriptor Pointer Register 7
Queue Receive DMA Head Descriptor Pointer Register 8
Queue Receive DMA Head Descriptor Pointer Register 9
Queue Receive DMA Head Descriptor Pointer Register 10
Queue Receive DMA Head Descriptor Pointer Register 11
Queue Receive DMA Head Descriptor Pointer Register 12
Queue Receive DMA Head Descriptor Pointer Register 13
Queue Receive DMA Head Descriptor Pointer Register 14
Queue Receive DMA Head Descriptor Pointer Register 15
Reserved
Queue Receive DMA Completion Pointer Register 0
Queue Receive DMA Completion Pointer Register 1
Queue Receive DMA Completion Pointer Register 2
Queue Receive DMA Completion Pointer Register 3
Queue Receive DMA Completion Pointer Register 4
Queue Receive DMA Completion Pointer Register 5
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Specifications 155