DS99R124Q_14 Datasheet, PDF (4/31 Pages) Texas Instruments – 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter

DS99R124Q
SNLS318C – JANUARY 2010 – REVISED OCTOBER 2010
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PIN DESCRIPTIONS (continued)
Pin Name
Pin #
I/O, Type
Description
BISTM
30
I, LVCMOS BIST Mode Input – Optional
w/ pull-down BISTM = 1, selects Payload Error Mode
BISTM = 0, selects Pass / Fail Result-Only Mode
PASS
28
O, LVCMOS
PASS Output (BIST Mode) – Optional
PASS = 1, no errors detected
PASS = 0, errors detected
Leave open if unused. Route to a test point (pad) recommended.
Optional Serial Bus Control Interface
SCL
SDA
ID[x]
5
I, LVCMOS Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to V_DDIO.
4
I/O, LVCMOS Serial Control Bus Data Input / Output - Optional
Open Drain SDA requires an external pull-up resistor to V_DDIO.
16
I, Analog
Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 5.
Power and Ground
VDDL
6, 31
Power
Logic Power, 1.8 V ±5%
VDDA
38, 43
Power
Analog Power, 1.8 V ±5%
VDDP
8, 46, 47 Power
SSC Generator Power, 1.8 V ±5%
VDDTX
13
Power
FPD-Link Power, 3.3 V ±10%
VDDIO
25
Power
LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10%
GND
9, 14, 26,
32, 39, 44,
45, 48
Ground
Ground
DAP
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connected to the ground plane (GND) with at least 9 vias.
Block Diagram
CMF
DS99R124Q ± CONVERTER
SSCG
RIN+
RIN-
PDB
SCL
SCA
ID[x]
BISTEN
BISTM
OSS_SEL
LFMODE
Timing and
Control
3
Error
Detector
PLL
SSC[2:0]
OEN
VODSEL
TxOUT[2]
TxOUT[1]
TxOUT[0]
TxCLKOUT
OS[2:0]
PASS
LOCK
Figure 1. FPD-Link II to FPD-Link Convertor
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
4
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