DS99R124Q_14 Datasheet, PDF (15/31 Pages) Texas Instruments – 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter

DS99R124Q
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FPD-LINK II INPUT
SNLS318C – JANUARY 2010 – REVISED OCTOBER 2010
Common Mode Filter Pin (CMF) — Optional
The Des provides access to the center tap of the internal termination. A capacitor may be placed on this pin for
additional common-mode filtering of the differential pair. This can be useful in high noise environments for
additional noise rejection capability. A 4.7 µF capacitor may be connected to this pin to Ground.
OUTPUT INTERFACES (LVCMOS & FPD-LINK)
OS[2:0] LVCMOS Outputs
Additional signals maybe received across the serial link per PCLK. The over-sampled bits are restricted to be low
speed signals and should be less than 1/5 of the frequency of the PCLK. Signals should convey level information
only, as pulse width distrotion will occur by the over sampling technique and location of the sampling clock. The
three over sampled bits are exactly mapped to DS99R421's; and to DS90UR421 bits are: OS0 = DIN21, OS1 =
DIN22, and OS2 = DIN23.
CLOCK-DATA RECOVERY STATUS FLAG (LOCK) and OUTPUT STATE SELECT (OSS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to the serial input, LOCK is Low and the FPD-Link
interface state is determined by the state of the OSS_SEL pin.
After the DS99R124Q completes its lock sequence to the input serial data, the LOCK output is driven HIGH,
indicating valid data and clock recovered from the serial input is available on the FPD-Link outputs. The TxCLK
output is held at its current state at the change from OSC_CLK (if this is enabled via OSC_SEL) to the recovered
clock (or vice versa). Note that the FPD-Link outputs may be held in an inactive state (TRI-STATE) through the
use of the Output Enable pin (OEN).
If there is a loss of clock from the input serial stream, LOCK is driven Low and the state of the outputs are based
on the OSS_SEL setting (configuration pin or register).
PDB
L
L
H
H
H
H
INPUTS
OEN
X
X
L
L
H
H
Table 1. Output State Table
OSS_SEL
L
H
L
H
L
H
LOCK
Z
L
L
L
L
L
OUTPUTS
OTHER OUTPUTS
TxCLKOUT is TRI-STATE
TxOUT[2:0] areTRI-STATE
OS[2:0] are TRI-STATE
PASS is TRI-STATE
TxCLKOUT is TRI-STATE
TxOUT[2:0] areTRI-STATE
OS[2:0] are LOW
PASS is TRI-STATE
TxCLKOUT is TRI-STATE
TxOUT[2:0] areTRI-STATE
OS[2:0] are LOW
PASS is HIGH
TxCLKOUT is TRI-STATE
TxOUT[2:0] areTRI-STATE
OS[2:0] are LOW
PASS is LOW
TxCLKOUT is TRI-STATE
TxOUT[2:0] areTRI-STATE
OS[2:0] are TRI-STATE
PASS is HIGH
TxCLKOUT is TRI-STATE
TxOUT[2:0] areLOW
OS[2:0] are LOW
PASS is LOW
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