DS99R124Q_14 Datasheet, PDF (23/31 Pages) Texas Instruments – 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter

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1.8V
FB1
C3
FB2
C4
FB3
C5
DS99R124Q (CON)
VDDL
VDDTX
VDDL
VDDA
VDDA
VDDIO
VDDP
VDDP
VDDIO
C1
Serial
FPD-Link II
Interface
C2
Host
Control
R
C1 - C2 = 0.1 PF (50 WV)
C3 - C9 = 0.1 PF
C10 - C12 = 4.7 PF
C13 = > 10 PF
R = 10 k:
FB1 - FB5: Impedance = 1 k:
Low DC resistance (< 1:)
VDDP
C6
RIN+
RIN-
CMF
C10
BISTEN
BISTM
OE
PDB
C13
SCL
SDA
ID[X]
NC
2
8
GND
DAP (GND)
TxCLKOUT+
TxCLKOUT
-
TxOUT2+
TxOUT2-
TxOUT1+
TxOUT1-
TxOUT0+
TxOUT0-
OS[2]
OS[1]
OS[0]
LOCK
PASS
VODSEL
OSS_SEL
LFMODE
SSC[2]
SSC[1]
SSC[0]
DS99R124Q
SNLS318C – JANUARY 2010 – REVISED OCTOBER 2010
3.3V
FB4
C7
VDDIO
FB5
C8
C9
FPD-Link
Interface
LVDS
100 Ohm
Termination
Tie to
desired
setting
Figure 24. DS99R124Q Typical Connection Diagram — Pin Control
POWER UP REQUIREMENTS AND PDB PIN
The VDD (V_DDn), V_DDTX and V_DDIO supply ramps should be faster than 1.5 ms with a monotonic rise. Supplies
may power up in any order, however device operation should be initiated only after all supplies are in their valid
operating ranges. The optional serial bus address selection is done upon power up also. Thus, if using this
optional feature, the PDB signal must be delayed to allow time for the ID setting to occur. The delay maybe done
by simply holding the PDB pin at a Low, or with an external RC delay based off the V_DDIO rail which would then
need to lag the others in time. If the PDB pin is pulled to V_DDIO, it is recommended to use a 10 kΩ pull-up and a
10 uF cap to GND to delay the PDB input signal.
Copyright © 2010, Texas Instruments Incorporated
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