DS99R124Q_14 Datasheet, PDF (22/31 Pages) Texas Instruments – 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter

DS99R124Q
SNLS318C – JANUARY 2010 – REVISED OCTOBER 2010
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Table 6. DS99R124Q — Serial Bus Control Registers (continued)
ADD ADD Register Name
(dec) (hex)
3
3 Des Features 2
Bit(s)
7:5
R/W Defau Function
lt
(bin)
R/W 000 EQ Gain
4
R/W 0 EQ Enable
3
R/W 0 Reserved
2:0 R/W 000 SSC
Applications Information
Description
000: ~1.625 dB
001: ~3.25 dB
010: ~4.87 dB
011: ~6.5 dB
100: ~8.125 dB
101: ~9.75 dB
110: ~11.375 dB
111: ~13 dB
0: EQ = disabled
1: EQ = enabled
Reserved
IF LFMODE = 0, then:
000: SSCG OFF
001: fdev = ±0.9%, fmod = CLK/2168
010: fdev = ±1.2%, fmod = CLK/2168
011: fdev = ±1.9%, fmod = CLK/2168
100: fdev = ±2.3%, fmod = CLK/2168
101: fdev = ±0.7%, fmod = CLK/1300
110: fdev = ±1.3%, fmod = CLK/1300
111: fdev = ±1.57%, fmod = CLK/1300
IF LFMODE = 1, then:
000: SSCG OFF
001: fdev = ±0.7%, fmod = CLK/625
010: fdev = ±1.3%, fmod = CLK/625
011: fdev = ±1.8%, fmod = CLK/625
100: fdev = ±2.2%, fmod = CLK/625
101: fdev = ±0.7%, fmod = CLK/385
110: fdev = ±1.2%, fmod = CLK/385
111: fdev = ±1.7%, fmod = CLK/385
DISPLAY APPLICATION
The DS99R124Q, in conjunction with the DS99R421Q or DS90UR241Q, is intended for interfacing between a
host (graphics processor) and a Display. It supports an 18-bit color depth (RGB666) and up to WVGA display
formats. In a RGB666 application, 18 color bits (R[5:0], G[5:0], B[5:0]), Pixel Clock (PCLK) and three control bits
(VS, HS and DE) are supported across the serial link with PCLK rates from 5 to 43MHz.
TYPICAL APPLICATION CONNECTION
Figure 24 shows a typical application of the DS99R124QQ Des in pin mode for a 43 MHz WVGA Display
Application. The LVDS inputs utilize 100 nF coupling capacitors to the line and the Receiver provides internal
termination. Bypass capacitors are placed near the power supply pins. Ferrite beads are placed on the power
lines for effective noise suppression.
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