DS125BR800A Datasheet, PDF (4/53 Pages) Texas Instruments – Low-Power 12.5-Gbps 8-Channel (Unidirectional) Repeater With Input Equalization

DS125BR800A
SNLS467 – NOVEMBER 2013
Pin Name
Pin Number
Differential High Speed I/O's
INB_0+, INB_0-,INB_1+,
INB_1-,INB_2+, INB_2-
,INB_3+, INB_3-
1, 2, 3, 4,
5, 6, 7, 8,
INA_0+, INA_0-,INA_1+,
INA_1-,INA_2+, INA_2-
,INA_3+, INA_3-
10, 11, 12, 13,
15, 16, 17, 18
OUTB_0+, OUTB_0-,
OUTB_1+, OUTB_1-,
OUTB_2+, OUTB_2-,
OUTB_3+, OUTB_3-
45, 44, 43, 42,
40, 39, 38, 37
OUTA_0+, OUTA_0-,
OUTA_1+, OUTA_1-,
OUTA_2+, OUTA_2-,
OUTA_3+, OUTA_3-
35, 34, 33, 32,
31, 30, 29, 28
Control Pins — Shared (LVCMOS)
ENSMB
48
ENSMB = 1 (SMBUS MODE)
SCL
50
SDA
49
AD0-AD3
54, 53, 47, 46
READ_EN
26
ENSMB = 0 (PIN MODE)
EQA0, EQA1,
EQB0, EQB1
20, 19,
46, 47
DEMA0, DEMA1,
DEMB0, DEMB1
49, 50,
53, 54
MODE
21
Table 1. Pin Descriptions⁽¹⁾
I/O, Type
Pin Description
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I
Inverting and non-inverting CML differential inputs to the equalizer. On-
chip 50Ω termination resistor connects INB_n+ to VDD and INB_n- to
VDD when enabled.
AC coupling required on high-speed I/O
I
Inverting and non-inverting CML differential inputs to the equalizer. On-
chip 50Ω termination resistor connects INA_n+ to VDD and INA_n- to
VDD when enabled.
AC coupling required on high-speed I/O
O
Inverting and non-inverting 50Ω driver outputs with de-emphasis.
Compatible with AC coupled CML inputs.
AC coupling required on high-speed I/O
O
Inverting and non-inverting 50Ω driver outputs with de-emphasis.
Compatible with AC coupled CML inputs.
AC coupling required on high-speed I/O
I, 4-LEVEL
System Management Bus (SMBus) enable pin
Tie 1kΩ to VDD = Register Access SMBus Slave Mode
FLOAT = Read External EEPROM (Master SMBUS Mode)
Tie 1kΩ to GND = Pin Mode
I, LVCMOS
O, OPEN Drain
I, LVCMOS,
O, OPEN Drain
I, LVCMOS
I, LVCMOS
ENSMB Master or Slave mode
SMBUS clock input is enabled (slave mode).
Clock output when loading EEPROM configuration (master mode).
ENSMB Master or Slave mode
The SMBus bidirectional SDA pin is enabled. Data input or open drain
(pull-down only) output.
ENSMB Master or Slave mode
SMBus Slave Address Inputs. In SMBus mode, these pins are the user
set SMBus slave address inputs.
When using an External EEPROM, a transition from high to low starts
the load from the external EEPROM
I, 4-LEVEL
I, 4-LEVEL
I, 4-LEVEL
EQA[1:0] and EQB[1:0] control the level of equalization on the input pins.
The pins are active only when ENSMB is de-asserted (low). The 8
channels are organized into two banks. Bank A is controlled with the
EQA[1:0] pins and bank B is controlled with the EQB[1:0] pins. When
ENSMB goes high the SMBus registers provide independent control of
each channel. The EQB[1:0] pins are converted to SMBUS AD2/AD3
inputs. See Table 3.
DEMA[1:0] and DEMB[1:0] control the level of de-emphasis of the output
driver. The pins are only active when ENSMB is de-asserted (low). The 8
channels are organized into two banks. Bank A is controlled with the
DEMA[1:0] pins and bank B is controlled with the DEMB[1:0] pins. When
ENSMB goes high the SMBus registers provide independent control of
each channel. The DEMA[1:0] pins are converted to SMBUS SCL/SDA
and DEMB[1:0] pins are converted to AD0, AD1 inputs.
See Table 4.
MODE control pin selects operating modes.
Tie 1kΩ to GND = GEN 1,2 and SAS/SATA (up to 6 Gbps)
FLOAT = AUTO Rate Select (for PCIe)
Tie 20kΩ to GND = SAS-3 and GEN-3 without De-emphasis
Tie 1kΩ to VDD = SAS-3 and GEN-3 with De-emphasis
See Table 7
(1) LVCMOS inputs without the "FLOAT" conditions must be driven to a logic low or high at all times or operation is not guaranteed.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
For 3.3V mode operation, VIN pin = 3.3V and the "VDD" for the 4-level input is 3.3V.
For 2.5V mode operation, VDD pin = 2.5V and the "VDD" for the 4-level input is 2.5V.
4
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