DS125BR800A Datasheet, PDF (35/53 Pages) Texas Instruments – Low-Power 12.5-Gbps 8-Channel (Unidirectional) Repeater With Input Equalization

DS125BR800A
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APPLICATIONS INFORMATION
SNLS467 – NOVEMBER 2013
GENERAL RECOMMENDATIONS
The DS125BR800A is a high performance circuit capable of delivering excellent performance. Careful attention
must be paid to the details associated with high-speed design as well as providing a clean power supply. Refer
to the information below and Revision 4 of the LVDS Owner's Manual for more detailed information on high
speed design tips to address signal integrity design issues.
SAS-3 and PCIe Gen-3 PLACEMENT WITHIN CHANNEL
SAS-3 and PCIe Gen-3 interfaces implement a training sequence between connected Tx and Rx pairs. While the
DS125BR800A circuitry is designed to be transparent for this training sequence and protocol, it is optimized for
receiver equalization. This linear equalization maximizes interconnect channel extension when the
DS125BR800A is placed with the majority of channel loss on the DS125BR800A input side. Adjustable transmit
de-emphasis and output voltage amplitude help to compensate for the remaining channel attenuation on the
output side.
When working with SAS-3 applications the maximum recommended input channel loss is -24 dB @ 6 GHz.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS
The CML inputs and outputs have been optimized to work with interconnects using a controlled differential
impedance of 85 - 100Ω. It is preferable to route differential lines exclusively on one layer of the board,
particularly for the input traces. The use of vias should be avoided if possible. If vias must be used, they should
be used sparingly and must be placed symmetrically for each side of a given differential pair. Whenever
differential vias are used the layout must also provide for a low inductance path for the return currents as well.
Route the differential signals away from other signals and noise sources on the printed circuit board. See AN-
1187 for additional information on QFN (WQFN) packages.
To minimize the effects of crosstalk, a 5:1 ratio or greater should be maintained between inter-pair and intra-pair
spacing.
EXTERNAL MICROSTRIP
20 mils
100 mils
20 mils
INTERNAL STRIPLINE
VDD
VDD
VDD
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
19
54
20
53
21
52
22
51
23
BOTTOM OF PKG
50
GND
24
49
25
48
26
47
27
46
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
VDD
VDD
Figure 7. Typical Routing Options
Copyright © 2013 , Texas Instruments Incorporated
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