DS125BR800A Datasheet, PDF (14/53 Pages) Texas Instruments – Low-Power 12.5-Gbps 8-Channel (Unidirectional) Repeater With Input Equalization

DS125BR800A
SNLS467 – NOVEMBER 2013
PWDN
(PIN 52)
0
0
RXDET
(PIN 22)
0
Tie 20kΩ
to GND
0
Float
(Default)
0
1
1
X
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Table 5. RX-Detect Settings
SMBus REG
bit [3:2]
00
01
10
11
Input Termination
Recommeded
Use
Comments
Hi-Z
X
Manual RX-Detect, input is high impedance mode
Pre Detect: Hi-Z
Post Detect: 50 Ω
PCIe Only
Auto RX-Detect, outputs test every 12 msec for
600 msec then stops; termination is Hi-Z until
detection; once detected input termination is 50 Ω
Reset function by pulsing PWDN high for 5 usec
then low again
Pre Detect: Hi-Z
Post Detect: 50 Ω
PCIe Only
Auto RX-Detect, outputs test every 12 msec until
detection occurs; termination is Hi-Z until RX
detection; once detected input termination is 50 Ω
50 Ω
All Others Manual RX-Detect, input is 50 Ω
High Impedance
X
Power down mode, input is Hi-Z, output drivers
are disabled
Used to reset RX-Detect State Machine when held
high for 5 usec
RX-Detect in SAS/SATA Applications
Unlike PCIe systems, SAS/SATA systems use a low speed Out-Of-Band or OOB communications sequence to
detect and communicate between Controllers/Expanders and target drives. This communication eliminates the
need to detect for endpoints like PCIe. For SAS systems, it is recommended to tie the RXDET pin high. This will
ensure any OOB sequences sent from the Controller/Expander will reach the target drive without any additional
latency due to the termination detection sequence defined by PCIe.
Table 6. OOB and Signal Detect Threshold Level⁽¹⁾
SD_TH
(PIN 26)
0
R
F
(default)
1
SMBus REG bit [3:2] and
[1:0]
10
01
00
11
[3:2] Assert Level (mVp-p)
3 Gbps
12 Gbps
18
75
12
40
[1:0] De-assert Level (mVp-p)
3 Gbps
12 Gbps
14
55
8
22
15
50
11
37
16
58
12
45
(1) VDD = 2.5V, 25°C, 11 00 11 00 pattern at 3 Gbps and 101010 pattern at 12 Gbps
MODE
(PIN 21)
0
R
F (default)
1
Table 7. MODE Operation With Pin Control
Driver Characteristics
Limiting
Transparent without DE
Automatic
Transparent with DE
PCIe
X
SAS
SATA
X (≤ 6G)
10GbE
X
X (SAS-3)
CPRI
OBSAI
X
SRIO
(R)XAUI
X
Interlaken
Infiniband
X
MODE operation with SMBus Registers
When in SMBus mode (Slave or Master), the MODE pin retains control of the output driver characteristics. In
order to override this control function, Register 0x08[2] must be written with a "1". Writting this bit enables MODE
control of each channel individually using the channel registers defined in Table 11.
14
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