DS125BR800A Datasheet, PDF (23/53 Pages) Texas Instruments – Low-Power 12.5-Gbps 8-Channel (Unidirectional) Repeater With Input Equalization

DS125BR800A
www.ti.com
SNLS467 – NOVEMBER 2013
Address
0x00
0x01
0x02
0x04
0x05
0x06
0x07
0x08
Table 11. SMBUS Slave Mode Register Map
Register Name
Observation,
Reset
Bit (s) Field
7
Reserved
6:3 Address Bit
AD[3:0]
PWDN Channels
2
EEPROM Read
Done
1
Reserved
0
Reserved
7:0 PWDN CHx
Override
PWDN Control
EQ Limiting
7:1 Reserved
0
Override PWDN
7:0 EQ Control
Slave Mode CRC Bits 7:0
Slave Register
7:5
Control
4
3
CRC bits
Reserved
Reserved
Register Enable
Digital Reset and
Control
Override
Pin Control
2:0 Reserved
7
Reserved
6
Reset Registers
5
Reset SMBus
Master
4:0 Reserved
7
Reserved
6
Override SD_TH
5
Reserved
4
Override IDLE
3
Override RXDET
2
Override MODE
1
Reserved
0
Reserved
Type
R/W
R
Default
0x00
R
R/W
R/W
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x10
R/W 0x01
Description
Set bit to 0.
Observation of AD[3:0] bit
[6]: AD3
[5]: AD2
[4]: AD1
[3]: AD0
1: Device completed the read from external
EEPROM.
Set bit to 0.
Set bit to 0.
Power Down per Channel
[7]: CH7 – CHA_3
[6]: CH6 – CHA_2
[5]: CH5 – CHA_1
[4]: CH4 – CHA_0
[3]: CH3 – CHB_3
[2]: CH2 – CHB_2
[1]: CH1 – CHB_1
[0]: CH0 – CHB_0
00'h = all channels enabled
FF'h = all channels disabled
Note: override PWDN pin.
Set bits to 0.
1: Block PWDN pin control
0: Allow PWDN pin control
CH7 - CH0 EQ Limiting Control
1 = EQ Limits
0 = EQ Linear (Default)
CRC bits [7:0]
Set bits to 0.
Set bit to 1.
1: Enables high speed channel control via SMBus
registers without CRC
0: Channel control via SMBus registers requires
correct CRC in Reg 0x05
Note: In order to change VOD, DEM and EQ of the
channels in slave mode without also setting CRC
each time, set this bit to 1.
Set bits to 0.
Set bit to 0.
Self clearing reset for SMBus registers. Writing a [1]
will return register settings to default values
Self clearing reset to SMBus master state machine
R/W 0x00
Set bits to 0 0001'b.
Set bit to 0.
1: Block SD_TH pin control
0: Allow SD_TH pin control
Set bit to 0.
1: IDLE control by registers
0: IDLE control by signal detect
1: Block RXDET pin control
0: Allow RXDET pin control
1: Block MODE pin control
0: Allow MODE pin control
Set bit to 0.
Set bit to 0.
Copyright © 2013 , Texas Instruments Incorporated
Product Folder Links: DS125BR800A
Submit Documentation Feedback
23