DRV8806 Datasheet, PDF (4/18 Pages) Texas Instruments – QUAD SERIAL INTERFACE LOW-SIDE DRIVER IC

DRV8806
SLVSBA3 – JUNE 2012
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) ^{(1) (2)}
VALUE
UNIT
VM
Power supply voltage range
–0.3 to 43
V
VOUTx
Output voltage range
–0.3 to 43
V
VCLAMP Clamp voltage range
–0.3 to 43
V
SDATOUT,
nFAULT
Output current
Peak clamp diode current⁽³⁾
DC or RMS clamp diode current⁽³⁾
20
mA
2
A
1
A
Digital input pin voltage range
–0.5 to 7
V
SDATOUT,
nFAULT
Digital output pin voltage range
–0.5 to 7
V
Peak motor drive output current, t < 1 μS
Continuous total power dissipation⁽³⁾
T_J
Operating virtual junction temperature range⁽³⁾
T_stg
Storage temperature range
Internally limited
A
See Thermal Information table
–40 to 150
°C
–60 to 150
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) Power dissipation and thermal limits must be observed.
THERMAL INFORMATION
THERMAL METRIC⁽¹⁾
θ_JA
θ_JCtop
θ_JB
ψ_JT
ψ_JB
θ_JCbot
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case (top) thermal resistance⁽³⁾
Junction-to-board thermal resistance⁽⁴⁾
Junction-to-top characterization parameter⁽⁵⁾
Junction-to-board characterization parameter⁽⁶⁾
Junction-to-case (bottom) thermal resistance⁽⁷⁾
DRV8806
PWP
16 PINS
39.6
24.6
20.3
0.7
20.1
2.3
UNITS
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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