66AK2H14_17 Datasheet, PDF(39/355 Page) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

66AK2H14_17 Datasheet, PDF (39/355 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

◁

66AK2H14/12/06

Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

SPRS866EâNovember 2013

Table 5-2

Terminal Functions â Signals and Control by Function (Part 2 of 20)

Signal Name

BOOTMODE00â

Ball No. Type IPD/IPU Description

B30

I

Down

BOOTMODE01â

D29

I

Down

BOOTMODE02â

A35

I

Down

BOOTMODE03â

B29

I

Down

BOOTMODE04â

E29

I

Down

BOOTMODE05â

BOOTMODE06â

BOOTMODE07â

D30

I

Down User defined Boot Mode pins

C30

I

Down See 8.1.2 ââBoot Modes Supportedââ on page 205 for more details.

A30

I

Down (â Pins are secondary functions and are shared with GPIO[01:13])

BOOTMODE08â

G30

I

Down

BOOTMODE09â

F31

I

Down

BOOTMODE10â

E30

I

Down

BOOTMODE11â

F30

I

Down

BOOTMODE12â

A31

I

Down

BOOTMODE13â

F24

BOOTMODE14â

E24

BOOTMODE15â

D24

BOOTCOMPLETE

AF5

DDR3A_REMAP_ENâ A36

LENDIANâ

F29

I

User defined Boot Mode pins

I

See 8.1.2 ââBoot Modes Supportedââ on page 205 for more details.

I

(â Pins are secondary functions and are shared with CORESEL[0:2])

OZ Down Boot progress indication output

I

Down Control ARM remapping of DDR3A address space in the lower 4 GB (32b space) Mode select.

Secondary function. Pin shared with GPIO16.

I

Up

Little endian configuration pin. Pin shared with GPIO00

MAINPLLODSELâ

ALTCORECLKN

ALTCORECLKP

ARMCLKN

ARMCLKP

CORECLKSEL

CORESEL0

CORESEL1

CORESEL2

CORESEL3

DDR3ACLKN

DDR3ACLKP

DDR3BCLKN

DDR3BCLKP

HOUT

HYP0CLKN

HYP0CLKP

LRESET

LRESETNMIEN

HYP1CLKN

HYP1CLKP

NMI

E32

AL2

AM2

B37

C37

AL4

F24

E24

D24

G24

A25

B25

AR39

AR38

AE5

AT10

AT9

AE4

AD4

AW5

AW4

AD5

I

Down Main PLL Output divider select. Pin shared with GPIO14.

Clock / Reset

I

Alternate clock input to Main PLL

I

I

Reference clock to drive ARM CorePac PLL

I

I

Down Core clock select to select between SYSCLK(N|p) and ALTCORECCLK to the main PLL

I

Down

I

Down

Select for the target core for LRESET and NMI

I

Down

I

Down

I

DDR3A reference clock input to DDR PLL

I

I

DDR3B reference clock input to DDR PLL

I

OZ Up

Interrupt output pulse created by IPCGRH

I

HyperLink reference clock to drive HyperLink0 SerDes

I

I

Up

Warm reset

I

Up

Enable for core selects

I

HyperLink reference clock to drive HyperLink 1 SerDes

I

I

Up

Non-maskable interrupt

Copyright 2013 Texas Instruments Incorporated

Submit Documentation Feedback

Terminals 39

▷