66AK2H14_17 Datasheet, PDF (10/355 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

List of Figures
66AK2H14/12/06
SPRS866E—November 2012—Revised November 2013
Figure 1-1
Figure 1-2
Figure 1-3
Figure 2-1
Figure 3-1
Figure 3-2
Figure 3-3
Figure 3-4
Figure 3-5
Figure 4-1
Figure 4-2
Figure 4-3
Figure 4-4
Figure 5-1
Figure 5-2
Figure 5-3
Figure 5-4
Figure 5-5
Figure 5-6
Figure 6-1
Figure 6-2
Figure 6-3
Figure 6-4
Figure 6-5
Figure 7-1
Figure 7-2
Figure 7-3
Figure 7-4
Figure 7-5
Figure 7-6
Figure 7-7
Figure 7-8
Figure 8-1
Figure 8-2
Figure 8-3
Figure 8-4
Figure 8-5
Figure 8-6
Figure 8-7
Figure 8-8
Figure 8-9
Functional Block Diagram for 66AK2H14 . . . . . .4
Functional Block Diagram for 66AK2H12 . . . . . .5
Functional Block Diagram for 66AK2H06 . . . . . .6
66AK2H14/12/06 Device Nomenclature . . . . . 18
C66x CorePac Block Diagram . . . . . . . . . . . . . . . 20
L1P Memory Configurations . . . . . . . . . . . . . . . . 21
L1D Memory Configurations . . . . . . . . . . . . . . . . 22
L2 Memory Configurations . . . . . . . . . . . . . . . . . 23
CorePac Revision ID Register (MM_REVID) . . . 26
66AK2H12 ARM CorePac Block Diagram . . . . . 27
66AK2H06 ARM CorePac Block Diagram . . . . . 28
ARM Interrupt Controller for Two Cortex-A15
Processor Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
ARM Interrupt Controller for Four Cortex-A15
Processor Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
AAW 1517-PIN BGA Package (Bottom View) . 33
Pin Map Panels (Bottom View) . . . . . . . . . . . . . . 33
66AK2H14/12/06 Pin Map Left Side Panel (A) —
Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
66AK2H14/12/06 Pin Map Left Center Panel (B)
— Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
66AK2H14/12/06 Pin Map Right Center Panel (C)
— Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
66AK2H14/12/06 Pin Map Right Side Panel (D)
— Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Programmable Range n Start Address Register
(PROGn_MPSAR) . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Programmable Range n End Address Register
(PROGn_MPEAR) . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Programmable Range n Memory Protection
Page Attribute Register (PROGn_MPPAR). . . 106
66AK2H14/12 Interrupt Topology . . . . . . . . . . 111
66AK2H06 Interrupt Topology . . . . . . . . . . . . . 112
TeraNet 3_A-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
TeraNet 3_A-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
TeraNet 3_C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
TeraNet C66x to SDMA . . . . . . . . . . . . . . . . . . . . 193
TeraNet 3P_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
TeraNet 3P_B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
TeraNet 6P_B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
TeraNet 3P_Tracer. . . . . . . . . . . . . . . . . . . . . . . . . 198
DEVSTAT Boot Mode Pins ROM Mapping . . . 206
Sleep Boot Mode Configuration Fields . . . . . 208
I²C Passive Mode Device Configuration
Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
I²C Master Mode Device Configuration
Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
SPI Device Configuration Fields . . . . . . . . . . . . 210
EMIF Boot Device Configuration Fields . . . . . 211
NAND Boot Device Configuration Fields. . . . 212
Serial Rapid I/O Boot Device Configuration
Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Ethernet (SGMII) Boot Device Configuration
Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 8-10
Figure 8-11
Figure 8-12
Figure 8-13
Figure 8-14
Figure 8-15
Figure 8-16
Figure 8-17
Figure 8-18
Figure 8-19
Figure 8-20
Figure 8-21
Figure 8-22
Figure 8-23
Figure 8-24
Figure 8-25
Figure 8-26
Figure 8-27
Figure 8-28
Figure 8-29
Figure 8-30
Figure 8-31
Figure 8-32
Figure 8-33
Figure 8-34
Figure 8-35
Figure 8-36
Figure 8-37
Figure 8-38
Figure 8-39
Figure 8-40
Figure 8-41
Figure 8-42
Figure 8-43
Figure 10-1
Figure 10-2
Figure 10-3
Figure 10-4
Figure 10-5
Figure 10-6
Figure 10-7
Figure 10-8
Figure 10-9
PCIe Boot Device Configuration Fields . . . . . .216
HyperLink Boot Device Configuration Fields 217
UART Boot Mode Configuration Field
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
Device Status Register. . . . . . . . . . . . . . . . . . . . . .234
Device Configuration Register (DEVCFG) . . . .235
JTAG ID (JTAGID) Register . . . . . . . . . . . . . . . . . .235
LRESETNMI PIN Status Register
(LRSTNMIPINSTAT) . . . . . . . . . . . . . . . . . . . . . . . . .236
LRESETNMI PIN Status Clear Register
(LRSTNMIPINSTAT_CLR) . . . . . . . . . . . . . . . . . . . .237
Reset Status Register (RESET_STAT) . . . . . . . . .238
Reset Status Clear Register
(RESET_STAT_CLR) . . . . . . . . . . . . . . . . . . . . . . . . .239
Boot Complete Register (BOOTCOMPLETE). .239
Power State Control Register
(PWRSTATECTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
NMI Generation Register (NMIGRx) . . . . . . . . .242
IPC Generation Registers (IPCGRx) . . . . . . . . . .242
IPC Acknowledgement Registers (IPCARx) . .243
IPC Generation Registers (IPCGRH) . . . . . . . . . .244
IPC Acknowledgement Register (IPCARH) . . .244
Timer Input Selection Register (TINPSEL) . . . .245
Timer Output Selection Register
(TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
Reset Mux Register . . . . . . . . . . . . . . . . . . . . . . . . .249
Device Speed Register (DEVSPEED) . . . . . . . . .250
ARM Endian Configuration Register 0
(ARMENDIAN_CFGr_0), r=0..7. . . . . . . . . . . . . . .251
ARM Endian Configuration Register 1
(ARMENDIAN_CFGr_1), r=0..7. . . . . . . . . . . . . . .251
ARM Endian Configuration Register 2
(ARMENDIAN_CFGr_2), r=0..7. . . . . . . . . . . . . . .252
Chip Miscellaneous Control Register
(CHIP_MISC_CTL0) . . . . . . . . . . . . . . . . . . . . . . . . .252
Chip Miscellaneous Control Register
(CHIP_MISC_CTL1) . . . . . . . . . . . . . . . . . . . . . . . . .253
System Endian Status Register . . . . . . . . . . . . . .253
SYNECLK_PINCTL Register. . . . . . . . . . . . . . . . . .254
USB_PHY_CTL0 Register. . . . . . . . . . . . . . . . . . . .254
USB_PHY_CTL1 Register. . . . . . . . . . . . . . . . . . . .256
USB_PHY_CTL2 Register. . . . . . . . . . . . . . . . . . . .257
USB_PHY_CTL3 Register. . . . . . . . . . . . . . . . . . . .258
USB_PHY_CTL4 Register. . . . . . . . . . . . . . . . . . . .259
USB_PHY_CTL5 Register. . . . . . . . . . . . . . . . . . . .260
Core Before IO Power Sequencing . . . . . . . . . .270
IO-Before-Core Power Sequencing. . . . . . . . . .272
SmartReflex 4-Pin 6-bit VID Interface Timing275
RESETFULL Reset Timing . . . . . . . . . . . . . . . . . . .287
Soft/Hard Reset Timing. . . . . . . . . . . . . . . . . . . . .287
Boot Configuration Timing . . . . . . . . . . . . . . . . .288
Main PLL and PLL Controller . . . . . . . . . . . . . . . .289
PLL Secondary Control Register (SECCTL) . . .293
PLL Controller Divider Register (PLLDIVn) . . .294
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and
other important disclaimers. PRODUCTION DATA.