66AK2H14_17 Datasheet, PDF (178/355 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

66AK2H14/12/06
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS866E—November 2013
6.4 Enhanced Direct Memory Access (EDMA3) Controller for 66AK2H14/12/06
The primary purpose of the EDMA3 is to service user-programmed data transfers between two memory-mapped
slave endpoints on the device. The EDMA3 services software-driven paging transfers (e.g., data movement between
external memory and internal memory), performs sorting or subframe extraction of various data structures, services
event driven peripherals, and offloads data transfers from the device C66x DSP CorePac or the ARM CorePac.
There are 5 EDMA channel controllers on the device:
• EDMA3CC0 has two transfer controllers: TPTC0 and TPTC1
• EDMA3CC1 has four transfer controllers: TPTC0, TPTC1, TPTC2, and TPTC3
• EDMA3CC2 has four transfer controllers: TPTC0, TPTC1, TPTC2, and TPTC3
• EDMA3CC3 has two transfer controllers: TPTC0 and TPTC1
• EDMA3CC4 has two transfer controllers: TPTC0 and TPTC1
In the context of this document, TPTCx is associated with EDMA3CCy, and is referred to as EDMA3CCy TPTCx.
Each of the transfer controllers has a direct connection to the switch fabric. Section 7.2 ‘‘Switch Fabric Connections
Matrix - Data Space’’ on page 187 lists the peripherals that can be accessed by the transfer controllers.
EDMA3CC0 is optimized to be used for transfers to/from/within the MSMC and DDR3A/DDR3B subsytems. The
others are used for the remaining traffic.
Each EDMA3 channel controller includes the following features:
• Fully orthogonal transfer description
– 3 transfer dimensions:
› Array (multiple bytes)
› Frame (multiple arrays)
› Block (multiple frames)
– Single event can trigger transfer of array, frame, or entire block
– Independent indexes on source and destination
• Flexible transfer definition:
– Increment or FIFO transfer addressing modes
– Linking mechanism allows for ping-pong buffering, circular buffering, and repetitive/continuous
transfers, all with no CPU intervention
– Chaining allows multiple transfers to execute with one event
• 512 PaRAM entries for all EDMA3CC:
– Used to define transfer context for channels
– Each PaRAM entry can be used as a DMA entry, QDMA entry, or link entry
• 64 DMA channels for all EDMA3CC:
– Manually triggered (CPU writes to channel controller register)
– External event triggered
– Chain triggered (completion of one transfer triggers another)
• 8 Quick DMA (QDMA) channels per EDMA3CCx:
– Used for software-driven transfers
– Triggered upon writing to a single PaRAM set entry
• Two transfer controllers and two event queues with programmable system-level priority for EDMA3CC0,
EDMA3CC3, and EDMA3CC4
178 Memory, Interrupts, and EDMA for 66AK2H14/12/06
Copyright 2013 Texas Instruments Incorporated
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