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66AK2H14_17 Datasheet, PDF (1/355 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC) | |||
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66AK2H14/12/06
SPRS866EâNovember 2012âRevised November 2013
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
Check for Evaluation Modules (EVM): EVMK2H
1 66AK2H14/12/06 Features and Description
1.1 Features
⢠Eight (66AK2H14/12) or Four (66AK2H06) TMS320C66xâ¢
DSP Core Subsystems (C66x CorePacs), Each With
â Up to 1.2 GHz C66x Fixed/Floating-Point DSP Cores
⺠38.4 GMacs/Core for Fixed Point @ 1.2 GHz
⺠19.2 GFlops/Core for Floating Point @ 1.2 GHz
â Memory
⺠32K Byte L1P Per CorePac
⺠32K Byte L1D Per CorePac
⺠1024K Byte Local L2 Per CorePac
⢠ARM® Cortexâ¢-A15 MPCore⢠Processors Containing
Four (66AK2H14/12) or Two (66AK2H06) ARM
Cortex-A15 Cores
â Up to 1.4-GHz Cortex-A15 Processor Core Speed
â 4MB L2 Cache Memory Shared by All ARM CorePacs
â Full Implementation of ARMv7-A Architecture
Instruction Set
â 32KB L1 Instruction Cache and Data Cache per
Cortex-A15 Processor Core
â AMBA 4.0 AXI Coherency Extension (ACE) Master Port,
Connected to MSMC for Low Latency Access to
Shared MSMC SRAM
⢠Multicore Shared Memory Controller (MSMC)
â 6 MB MSM SRAM Memory Shared by DSP CorePacs
and ARM CorePac
â Memory Protection Unit for Both MSM SRAM and
DDR3_EMIF
⢠Multicore Navigator
â 16k Multi-Purpose Hardware Queues with Queue
Manager
â Packet-Based DMA for Zero-Overhead Transfers
⢠Network Coprocessor
â Packet Accelerator Enables Support for
⺠Transport Plane IPsec, GTP-U, SCTP, PDCP
⺠L2 User Plane PDCP (RoHC, Air Ciphering)
⺠1 Gbps Wire Speed Throughput at 1.5 MPackets Per
Second
â Security Accelerator Engine Enables Support for
⺠IPSec, SRTP, 3GPP and WiMAX Air Interface, and
SSL/TLS Security
⺠ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC,
GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1,
SHA-2 (256-bit Hash), MD5
⺠Up To 2.4 Gbps IPSec and 2.4 Gbps Air Ciphering
â Ethernet Subsystem
⺠Five-Port Switch (four SGMII ports)
⢠Peripherals
â Four Lanes of SRIO 2.1
⺠Supports Up To 5 GBaud
⺠Supports Direct I/O, Message Passing
â Two Lanes PCIe Gen2
⺠Supports Up To 5 GBaud
â TwoHyperLink
⺠Supports Connections to Other KeyStone
Architecture Devices Providing Resource
Scalability
⺠Supports Up To 50 GBaud
â 10-Gigabit Ethernet (10-GbE) Switch Subsystem
(66AK2H14 only)
⺠Two XFI Ports
⺠IEEE1588 Support
â Five Enhanced Direct Memory Access (EDMA)
Modules
â Two 72-Bit DDR3 Interfaces with Speeds Up To 1600
MHz
â EMIF16 Interface
â USB 3.0
â Two UART Interfaces
â Three I2C Interfaces
â 32 GPIO Pins
â Three SPI Interfaces
â Semaphore Module
â 64-Bit Timers
⺠Twenty 64-Bit Timers for 66AK2H14/12
⺠Fourteen 64-Bit Timers for 66AK206
â Five On-Chip PLLs
⢠Commercial Case Temperature:
â 0°C to 85°C
⢠Extended Case Temperature:
â - 40°C to 100°C
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and
other important disclaimers. PRODUCTION DATA.
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