MSP430FR4133 Datasheet, PDF (37/101 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430FR4133, MSP430FR4132, MSP430FR4131
SLAS865B – OCTOBER 2014 – REVISED AUGUST 2015
Table 6-2. Interrupt Sources, Flags, and Vectors (continued)
INTERRUPT SOURCE
eUSCI_B0 Receive or Transmit
ADC
P1
P2
LCD
Reserved
Signatures
INTERRUPT FLAG
UCB0RXIFG, UCB0TXIFG (SPI mode)
UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0,
UCRXIFG1, UCTXIFG1, UCRXIFG2,
UCTXIFG2, UCRXIFG3, UCTXIFG3,
UCCNTIFG, UCBIT9IFG (I2C mode)
(UCB0IV)
ADCIFG0, ADCINIFG, ADCLOIFG,
ADCHIIFG, ADCTOVIFG, ADCOVIFG
(ADCIV)
P1IFG.0 to P1IFG.7 (P1IV)
P2IFG.0 to P2IFG.7 (P2IV)
LCDBLKOFFIFG, LCDBLKONIFG,
LCDFRMIFG (LCDEIV)
Reserved
BSL Signature 2
BSL Signature 1
JTAG Signature 2
JTAG Signature 1
SYSTEM
INTERRUPT
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
WORD
ADDRESS
FFEAh
FFE8h
FFE6h
FFE4h
FFE2h
FFE0h-FF88h
0FF86h
0FF84h
0FF82h
0FF80h
PRIORITY
53
52
51
50
49, Lowest
6.4 Bootstrap Loader (BSL)
The BSL lets users program the FRAM or RAM using a UART serial interface. Access to the device
memory through the BSL is protected by an user-defined password. Use of the BSL requires four pins as
shown in Table 6-3. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and
TEST/SBWTCK pins. For a complete description of the features of the BSL and its implementation, see
the MSP430FR4xx and MSP430FR2xx Bootstrap Loader (BSL) User's Guide (SLAU610).
Table 6-3. BSL Pin Requirements and Functions
DEVICE SIGNAL
RST/NMI/SBWTDIO
TEST/SBWTCK
P1.0
P1.1
VCC
VSS
BSL FUNCTION
Entry sequence signal
Entry sequence signal
Data transmit
Data receive
Power supply
Ground supply
6.5 JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to
enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with
MSP430 development tools and device programmers. The JTAG pin requirements are shown in
Table 6-4. For further details on interfacing to development tools and device programmers, see the
MSP430 Hardware Tools User's Guide (SLAU278). For a complete description of the features of the JTAG
interface and its implementation, see MSP430 Programming Via the JTAG Interface (SLAU320).
Copyright © 2014–2015, Texas Instruments Incorporated
Detailed Description
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