TMS320DM6437_17 Datasheet, PDF (36/306 Pages) Texas Instruments – Digital Media Processor

TMS320DM6437
Digital Media Processor
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
www.ti.com
Table 2-11. EMIFA Terminal Functions (EMIFA Pinout Mode 3, AEM[2:0] = 011) (continued)
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE ⁽¹⁾
OTHER ^{(2) (3)}
DESCRIPTION
B0/LCD_FIELD/
EM_A[3]/GP[11]
B18
D21
I/O/Z
IPD
DV_DD33
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
For EMIFA, it is address bit 3 output EM_A[3].
B1/EM_A[2]/
(CLE)/GP[8]/
B16 A20
(AEAW0/PLLMS0)
I/O/Z
IPD
DV_DD33
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
For EMIFA, it is address bit 2 output EM_A[2].
G1/EM_A[1]/
(ALE)/GP[9]/
A16 B20
(AEAW1/PLLMS1)
I/O/Z
IPD
DV_DD33
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
For EMIFA, it is address output EM_A[1].
R1/ EM_A[0]/
GP[7]/(AEM2)
B17 C21
I/O/Z
IPD
DV_DD33
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
For EMIFA, this is Address output EM_A[0], which is the least
significant bit on a 32-bit word address.
For an 8-bit asynchronous memory, this pin is the 3rd bit of the
address.
EMIFA FUNCTIONAL PINS: 8-Bit NAND (EMIFA Pinout Mode 3, AEM[2:0] = 011)
G1/EM_A[1]/
(ALE)/GP[9]/
A16 B20
(AEAW1/PLLMS1)
I/O/Z
IPD
DV_DD33
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
When used for EMIFA (NAND) , this pin is the Address Latch Enable
output (ALE).
B1/EM_A[2]/
(CLE)/GP[8]/
B16 A20
(AEAW0/PLLMS0)
I/O/Z
IPD
DV_DD33
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
When used for EMIFA (NAND) , this pin is the Command Latch
Enable output (CLE).
EM_WAIT/
(RDY/BSY)
EM_OE
EM_WE
E15 D20
D15 D19
E14 C19
I/O/Z
I/O/Z
I/O/Z
IPU
DV_DD33
IPU
DV_DD33
IPU
DV_DD33
When used for EMIFA (NAND), it is ready/busy input (RDY/BSY).
When used for EMIFA (NAND), this pin is read enable output (RE).
When used for EMIFA (NAND), this pin is write enable output (WE).
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
G0/EM_CS2/
GP[12]
C19 C22
I/O/Z
IPD
DV_DD33
For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with
NAND flash.
This is the chip select for the default boot and ROM boot modes.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
LCD_OE/EM_CS3/
GP[13]
C18
D22
I/O/Z
IPD
DV_DD33
For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with
NAND flash.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
VSYNC/EM_CS4/
GP[32]
E19
H22
I/O/Z
IPD
DV_DD33
For EMIFA, it is Chip Select 4 output EM_CS4 for use with NAND
flash.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
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