TMS320DM6437_17 Datasheet, PDF (103/306 Pages) Texas Instruments – Digital Media Processor

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TMS320DM6437
Digital Media Processor
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
Table 3-19. PINMUX0 Register Descriptions (continued)
Bit
Field Name
Description
Pins Controlled
CI[3:2] Function Select.
0 = No CCDC CI[3:2].
Sub-Block 0
Pins function as PCI or GPIO or EMIFA based on AEM, AEAW, and PCIEN
CI3(CCD11)/EM_A[17]/AD31/EM_D[4]/GP[47]
settings (default).
28
CI32SEL
CI2(CCD10)/EM_A[18]/PRST/EM_D[5]/GP[46]
1 = Selects CCDC [3:2] (as CCD10 and CCD11, respectively) to get at least a
12-bit CCDC.
The combination of PINMUX0/1 fields AEM,
To use the 12-bit CCDC, the user must also configure PINMUX0.CCDCSEL = 1 AEAW, PCIEN, and CI32SEL bits control the
and PINMUX0.CI10SEL = 1.
pin muxing of these 2 pins. ⁽¹⁾
Not applicable (N/A) for AEM = 3 (011b), 4 (100b), or PCIEN = 1.
27
RSV
Reserved. For proper device operation, the user should only write "0" to this bit
(default).
CI[5:4] Function Select.
0 = No CCDC CI[5:4].
Sub-Block 0
Pins function as PCI or GPIO or EMIFA based on AEM, AEAW, and PCIEN
CI5(CCD13)/EM_A[15]/AD29/EM_D[2]/GP[49]
settings (default).
26
CI54SEL
CI4(CCD12)/EM_A[16]/PGNT/EM_D[3]/GP[48]
1 = Selects CCDC [5:4] (as CCD12 and CCD13, respectively) to get at least a
14-bit CCDC.
The combination of PINMUX0/1 fields AEM,
To use the 14-bit CCDC, the user must also configure PINMUX0.CCDCSEL = 1, AEAW, PCIEN, and CI54SEL bits control the
PINMUX0.CI10SEL = 1, and PINMUX0.CI32SEL = 1.
pin muxing of these 2 pins.⁽¹⁾
Not applicable (N/A) for AEM = 3 (011b), 4 (100b), or PCIEN = 1.
CI[7:6] Function Select.
0 = No CCDC CI[7:6].
Sub-Block 0
Pins function as PCI or GPIO or EMIFA based on AEM, AEAW, and PCIEN
CI7(CCD15)/EM_A[13]/AD25/EM_D[0]/GP[51]
settings (default).
25
CI76SEL
CI6(CCD14)/EM_A[14]/AD27/EM_D[1]/GP[50]
1 = Selects CCDC [7:6] (as CCD14 and CCD15, respectively) to get at least a
16-bit CCDC.
The combination of PINMUX0/1 fields AEM,
To use the 16-bit CCDC, the user must also configure PINMUX0.CCDCSEL = 1, AEAW, PCIEN, and CI76SEL bits control the
PINMUX0.CI10SEL = 1, PINMUX0.CI32SEL = 1, and PINMUX0.CI54SEL = 1.
pin muxing of these 2 pins.⁽¹⁾
Not applicable (N/A) for AEM = 3 (011b), 4 (100b), or PCIEN = 1.
CCDC Field Select.
24
CFLDSEL
0 = No CCDC Field (C_FIELD).
Pin functions as EMIFA EM_A[21] or GPIO based on AEM setting (default).
1 = CCDC Field (C_FIELD).
Sub-Block 0
C_FIELD/EM_A[21]/GP[34]
The combination of PINMUX0/1 fields
CFLDSEL and AEM control the muxing of this
pin. ⁽¹⁾
CCDC Write Enable Select.
0 = No CCDC Write Enable.
23
CWENSEL ^{Pin functions as EMIFA EM_R/W or GPIO based on AEM setting (default).}
1 = CCDC Write Enable (C_WE).
Pin functions as CCDC Write Enable C_WE.
Applicable only for AEM = 0 (000b), 4 (100b), or 5 (101b).
Sub-Block 0
C_WE/EM_R/W/GP[35]
The combination of PINMUX0 fields CWENSEL
and AEM control the muxing of this pin. ⁽¹⁾
CCDC HD and VD Select.
22
HVDSEL
0 = No CCDC HD and VD.
Pins function as GPIO (GP[53] and GP[52]) (default).
1 = CCDC HD and VD.
Sub-Block 0
VD/GP[53]
HD/GP[52]
The PINMUX0 field HVDSEL alone controls the
muxing of these 2 pins.
21
RSV
Reserved. For proper device operation, the user should only write "0" to this bit
(default).
Sub-Block 0
CCDC Select.
This bit field determines if CCDC is supported or not.
20
CCDCSEL
0 = CCDC not supported.
Pins function as GPIO (GP[54] and GP[43:36]) (default).
1 = CCDC supported.
Pins function as CCDC PCLK, YI[7:0].
PCLK/GP[54]
YI7(CCD7)/GP[43]
YI6(CCD6)/GP[42]
YI5(CCD5)/GP[41]
YI4(CCD4)/GP[40]
YI3(CCD3)/GP[39]
YI2(CCD2)/GP[38]
YI1(CCD1)/GP[37]
YI0(CCD0)/GP[36]
The PINMUX0 field CCDCSEL alone controls
the muxing of these 9 pins.
19
RSV
Reserved. For proper device operation, the user should only write "0" to this bit
(default).
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Device Configurations 103