TMS320DM6437_17 Datasheet, PDF (165/306 Pages) Texas Instruments – Digital Media Processor

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Power Domain
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TMS320DM6437
Digital Media Processor
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
Table 6-1. DM6437 Power and Clock Domains
Clock Domain
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
CLKDIV3
CLKDIV3
CLKDIV3
CLKDIV3
CLKDIV3
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV1
Peripheral/Module
UART0
UART1
HECC
I2C
Timer0
Timer1
Timer2
PWM0
PWM1
PWM2
DDR2
VPSS
EDMA
PCI
SCR
GPSC
LPSCs
PLLC1
PLLC2
Ice Pick
EMIFA
HPI
VLYNQ
EMAC
McASP0
McBSP0
McBSP1
GPIO
C64x+ CPU
Table 6-2. DM6437 Clock Domains
SUBSYSTEM
Peripherals (CLKIN Domain)
CLOCK DOMAIN
CLKIN
DOMAIN CLOCK
SOURCE
PLLC1 AUXCLK⁽¹⁾
FIXED RATIO vs.
SYSCLK1 FREQUENCY
–
DSP Subsystem
CLKDIV1
PLLC1 SYSCLK1
1:1
EDMA3
CLKDIV3
PLLC1 SYSCLK2
1:3
VPSS
CLKDIV3
PLLC1 SYSCLK2
1:3
Peripherals (CLKDIV3 Domain)
CLKDIV3
PLLC1 SYSCLK2
1:3
Peripherals (CLKDIV6 Domain)
CLKDIV6
PLLC1 SYSCLK3
1:6
(1) PLLC1 AUXCLK runs at exactly the same frequency as the device clock source from the MXI/CLKIN pin.
EXAMPLE
FREQUENCY (MHz)
27 MHz
594 MHz
198 MHz
198 MHz
198 MHz
99 MHz
The CLKDIV1:CLKDIV3:CLKDIV6 ratio must be strictly followed by programming the PLL Controller 1
(PLLC1) PLLDIV1, PLLDIV2, and PLLDIV3 registers appropriately (see Table 6-3).
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Peripheral Information and Electrical Specifications 165