TMS320DM6437_17 Datasheet, PDF (33/306 Pages) Texas Instruments – Digital Media Processor

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TMS320DM6437
Digital Media Processor
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
Table 2-10. EMIFA Terminal Functions (EMIFA Pinout Mode 1, AEM[2:0] = 001) (continued)
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE ⁽¹⁾
OTHER ^{(2) (3)}
DESCRIPTION
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
G0/EM_CS2/
GP[12]
C19 C22
I/O/Z
IPD
DV_DD33
For EMIFA (NAND), this pin is Chip Select 2 output EM_CS2 for use
with NAND flash.
This is the chip select for the default boot and ROM boot modes.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
LCD_OE/EM_CS3/
GP[13]
C18
D22
I/O/Z
IPD
DV_DD33
For EMIFA (NAND), this pin is Chip Select 3 output EM_CS3 for use
with NAND flash.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
VSYNC/EM_CS4/
GP[32]
E19
H22
I/O/Z
IPD
DV_DD33
For EMIFA (NAND), it is Chip Select 4 output EM_CS4 for use with
NAND flash.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
HSYNC/EM_CS5/
GP[33]
F19
J22
I/O/Z
COUT0/EM_D0/
GP[14]
D16
E21
COUT1/EM_D1/
GP[15]
D18
G20
COUT2/EM_D2/
GP[16]
D17
E22
COUT3/EM_D3/
GP[17]
E16
F20
COUT4/EM_D4/
GP[18]
E18
G21
COUT5/EM_D5/
GP[19]
E17
F22
COUT6/EM_D6/
GP[20]
F16
F21
COUT7/EM_D7/
GP[21]
F17
H20
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
For EMIFA (NAND), it is Chip Select 5 output EM_CS5 for use with
NAND flash.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
These pins are multiplexed between VPBE (VENC), EMIFA (NAND),
and GPIO.
For EMIFA (NAND) AEM[2:0] = 001, these are the 8-bit bi-directional
data bus (EM_D[7:0]).
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