TLC5955 Datasheet, PDF (35/53 Pages) Texas Instruments – TLC5955 48-Channel, 16-Bit, PWM LED Driver with DC, BC, LED Open-Short Detection, and Internal Current Setting

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TLC5955
SBVS237 – MARCH 2014
8.4.4.4 Display Timing Reset Function
The display timing reset function allows initializing the display timing with a LAT rising edge. This function can be
switched on or off with the TMGRST bit in the control data latch. When the TMGRST bit is 1, the GS counter is
reset to 0 and all outputs are forced off at the LAT rising edge for a GS data write. Furthermore, the 768-bit GS
data latch is updated with the data from the common shift register and the 336-bit DC data latch is updated with
the DC data in the 371-bit control data latch. When the TMGRST bit is 0, the GS counter is not reset and the
outputs are not forced off, even if a LAT rising edge is input. A timing diagram for this function is shown in
Figure 30.
Control Data Write (MSB of the Common Shift Register = 1)
Grayscale Data Write (MSB of the Common Shift Register = 0)
SIN
DCR0 DCR0 DCR0 DCR0
4A
3A
2A
1A
764 765 766 767 768
SCLK
DCR0
0A
769
Low
1
GSB15 GSB15
15A 14A
2
3
GSR0 GSR0 GSR0
3A
2A
1A
766 767 768
GSR0
0A
769
Grayscale Data Write
Low GSB15 GSB15 GSB15
15B 14B 13B
12
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LAT
GSCLK
DSPRPT Bit in Control Data
(Internal)
DSPRPT Bit = 1
TMGRST Bit in Control Data
(Internal)
TMGRST Bit = 1
RFRESH Bit in Control Data
(Internal)
RFRESH Bit = 0
Common Shift Register
(Internal)
GS Counter Data
(Internal)
GS counter data are incremented
at each GSCLK rising edge.
Internal LAT Enable
(Internal)
Always Enabled
Internal LAT Signal
(Internal)
GS Data Latch
(Internal)
Control Data Latch
(Internal)
Old Control Data
SID are loaded at the LAT falling edge.
0
GS counter data are incremented at each
GSCLK rising edge.
GS counter is reset to zero when LAT for
GS data writes is input with TMGRST = 1.
New Control Data
Old Grayscale Data
New Grayscale Data
DC Data Latch
(Internal)
OUTXn⁽¹⁾
OFF
ON
SOUT
High
Old DC Data
OUTXn are controlled by old GS, DC data.
New DC Data
OUTXn are forced off when LAT for GS data
writes is input with the TMGRST bit = 1.
OUTXn are controlled by new GS, DC data.
DCR0 DCR0 DCR0
2A
1A
0A
Low
LOD LOD LOD LOD
B15A G15A R15A B14A
Figure 30. Display Timing Reset Function (DSPRPT = 1, TMGRST = 1, and RFRESH = 0)
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