TLC5955 Datasheet, PDF (20/53 Pages) Texas Instruments – TLC5955 48-Channel, 16-Bit, PWM LED Driver with DC, BC, LED Open-Short Detection, and Internal Current Setting

TLC5955
SBVS237 – MARCH 2014
www.ti.com
SIN
R0
0A
Low
B15
15B
B15
14B
B15
13B
R0 R0 R0 R0
3B 2B 1B 0B
Low
B15
15C
B15
14C
B15
13C
B15
12C
B15
11C
SCLK
LAT
Common Shift Register LSB
R0
(Internal)
0A
Common Shift Register LSB+1
R0
(Internal)
1A
123
4
766 767 768 769
1
23
4
5
6
Low
B15
15B
B15
14B
R0
0A
Low
B15
15B
R0 R0 R0
3B 2B 1B
R0 R0 R0
4B 3B 2B
R0
0B
Low
B15
15C
B15 B15 B15
14C 13C 12C
R0
1B
R0
0B
Low
B15
15C
B15 B15
14C 13C
Common Shift Register MSB–2
(Internal)
Common Shift Register MSB–1
(Internal)
Common Shift Register MSB
(Internal)
B15 LOD LOD LOD LOD
14A
G15
R15 B14 G14
B15
LOD LOD LOD LOD
15A
B15 G15 R15 B14
Low
LOD LOD LOD
B15 G15 R15
R0
0A
Low
B15
15B
B15
14B
LOD
G15A
LOD LOD LOD LOD LOD
R15A B14A G14A R14A B13A
R0
1A
R0
0A
Low
B15
15B
LOD
B15A
LOD LOD LOD LOD LOD
G15A R15A B14A G14A R14A
R0 R0 R0
2A 1A 0A
Low
LOD LOD LOD LOD LOD
B15A G15A R15A B14A G14A
Grayscale Data Latch
(Internal)
Control Data Latch
(DC, MC, BC, FC)
(Internal)
336-Bit DC Data Latch
(Internal)
GS Data
DC, MC, BC, FC Data
DC Data
GS Data
Control data are not changed.
Same data are copied from the DC data latch in the control data latch.
SOUT
L
LOD LOD LOD
B15 G15 R15
R0 R0 R0
2A 1A 0A
Low
LOD LOD LOD LOD LOD
B15A G15A R15A B14A G14A
Figure 22. Grayscale Data Write Timing Diagram (RFRESH = 0)
8.3.2.3 Control Data Latch
The control data latch is 371 bits long. The data latch contains dot correction (DC) data, maximum current (MC)
data, global brightness control (BC) data, and function control (FC) data. The DC for each constant-current
output are controlled by the data in the DC data latch. The control data in the data latch are updated with the
lower 371 bits of the common shift register at the LAT rising edge when the common shift register MSB is 1. The
336 bits of DC data are copied from the control data latch when the 65,536th GSCLK is input with RFRESH set
to 1 in the control data latch after the GS data are written or the LAT rising edge for GS data writes is input when
the RFRESH bit is 0.
When the device is powered up, the data in the control data latch (except the MC bits) are random. Therefore,
DC, BC, and FC data must be written to the control data latch before turning on the constant-current outputs.
Furthermore, MC data should be set appropriately for the application. Refer to Figure 23 for a control data write
timing diagram.
20
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