TLC5955 Datasheet, PDF (21/53 Pages) Texas Instruments – TLC5955 48-Channel, 16-Bit, PWM LED Driver with DC, BC, LED Open-Short Detection, and Internal Current Setting

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TLC5955
SBVS237 – MARCH 2014
SIN
DCR0
0A
H
H
L
L
H
DCR0 DCR0 DCR0 DCR0
3B
2B
1B
0B
HH
L
DC, MC, BC, FC are selected
when the MSB is high.
SCLK
1
DC, MC, BC, FC data writes are selected when the MSB[1:9] bits are 96h (HLLHLHHL).
23
4
5
766 767 768 769
1
23
LH
L
4
5
6
LAT
Common Shift Register LSB
(Bit 0, Internal)
DCR0
0A
H
H
L
L
Common Shift Register LSB +1
(Bit 1, Internal)
DCR0
1A
DCR0
0A
H
H
L
DCR0 DCR0 DCR0
3B
2B
1B
DCR0 DCR0 DCR0
4B
3B
2B
DCR0
0B
DCR1
1B
H
H
L
L
H
DCR0
0B
H
H
L
L
Common Shift Register
(Bit 336, Internal)
MCR
0A
DCB0 DCB0 DCB0 DCB0
6A
5A
4A
3A
MCG MCR MCR
0B 2B 1B
MCR
0B
DCB0 DCB0 DCB0 DCB0 DCB0
6B
5B
4B
3B
2B
Common Shift Register
(Bit 344, Internal)
MCB
2A
MCB MCB MCG MCB
1A 0A 2A 1A
BCR BCR BCR
2B 1B 0B
MCB
2B
MCB MCB MCG MCG MCG
1B 0B 2B 1B 0B
Common Shift Register MSB–1
(Bit 767, Internal)
H
Common Shift Register MSB
(Bit 768, Internal)
H
L
L
H
L
H
L
L
H
DCR0 DCR0
1A
0A
H
H
L
L
H
L
H
DCR0 DCR0 DCR0
2A
1A
0A
H
H
L
L
H
L
GS Data Latch
(Internal)
DC Data in Control Data Latch
(Internal)
Old DC Data
336-Bit DC Data Latch
(Internal)
DC Data
MC Data Latch
(Internal)
Old MC Data
The 9-bit MC data (bits 344:336) in the data latch are not updated at this time
because the previous MC data (MCB2A to MCR0A) are written.
BC Data Latch
(Internal)
Old BC Data
FC Data Latch
(Internal)
Old FC Data
On and off control data are not changed.
DC data in the data latch are updated when the MSB of the common shift register
is 1 and the write command bit (bits 767 :760) is 96h (10010110b).
New DC Data
The 336-bit DC data are not updated at this time. DC data in the control data latch
are copied to the 336-bit DC data latch when the GS data are copied from common
shift register to the GS data latch.
DC Data are Not Changed
MC data are updated when the same data are written twice with the write command
data (96h). MCB2B to MCR0B data must be the same as MCB2A to MCR0A.
New MC Data
New BC Data
BC and FC data in the data latch are updated when the MSB of the common shift
register is 1 and write command bit (bits 767 :760) is 96h10010110b.
New FC Data
SOUT
H
H
L
L
H
DCR0 DCR0 DCR0
2
1
0
H
H
L
LH
L
Figure 23. Control Data Write Timing Diagram for DC, MC, BC, and FC
Copyright © 2014, Texas Instruments Incorporated
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