TLC5955 Datasheet, PDF (24/53 Pages) Texas Instruments – TLC5955 48-Channel, 16-Bit, PWM LED Driver with DC, BC, LED Open-Short Detection, and Internal Current Setting

TLC5955
SBVS237 – MARCH 2014
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8.3.3 Status Information Data (SID)
The status information data (SID) contains the status of the LED open detection (LOD) and LED short detection
(LSD). When the MSB of the common shift register is set to 0 and the RFRESH bit in the control data latch is 0,
the SID are loaded to the common shift register at the LAT falling edge after the data in the common shift
register are loaded to the grayscale data latch. If the common shift register MSB is 1, the SID are not loaded to
the common shift register.
When the MSB of the common shift register is set to 0 and the RFRESH bit in the control data latch is 1, the SID
are loaded to the common shift register at the GS counter 0000h just after LAT when the GS data are input. If
the common shift register MSB is 1, the SID are not loaded to the common shift register. When the RFRESH bit
is 1, the SCLK rising edge must be input with a low-level LAT signal after 65,538 GSCLKs (or more) are input
from the LAT rising signal input.
After being loaded into the common shift register, new SID data cannot be loaded until at least one new bit of
data is written into the common shift register. To recheck SID without changing the GS data, reprogram the
common shift register with the same data currently programmed into the GS latch. When LAT goes high, the GS
data do not change, but new SID data are loaded into the common shift register. LOD and LSD are shifted out of
SOUT with each SCLK rising edge. The SID load configuration is shown in Figure 24 and Table 6.
SID are loaded
to the common
shift register at
the LAT falling
edge when the
common shift
register MSB is 0.
LOD
Data of
OUTB15
LOD
Data of
OUTB0
LOD
Data of
OUTG0
LOD
LSD
Data of Data of
OUTR0 OUTB15
LSD
Data of
OUTB0
LSD
Data of
OUTG0
LSD
Data of
OUTR0
SOUT
MSB
Latch
Select
bit
Common
Data Bit
767
Common Common Common Common
Data Bit Data Bit Data Bit Data Bit
722
721
720
719
Common
Data Bit
674
Common
Data Bit
673
Common
Data Bit
672
LSB
Common
Data Bit
671-0
Common Shift Register (769 Bits)
Figure 24. SID Load Configuration
SIN
SCLK
24
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