AM5718_16 Datasheet, PDF (345/394 Pages) Texas Instruments – Sitara Processors Silicon Revision 2.0

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AM5718, AM5716
SPRS957C – MARCH 2016 – REVISED NOVEMBER 2016
Table 7-157. Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET1 Direct Input mode (continued)
BALL
E7
E8
D9
BALL NAME
vout1_d7
vout1_d8
vout1_d9
PR2_PRU0_DIR_IN_MANUAL1
A_DELAY (ps)
G_DELAY (ps)
0
0
0
0
0
0
CFG REGISTER
CFG_VOUT1_D7_IN
CFG_VOUT1_D8_IN
CFG_VOUT1_D9_IN
MUXMODE
12
pr2_pru0_gpi4
pr2_pru0_gpi5
pr2_pru0_gpi6
Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU0 IOSET2
Direct Input mode. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO
Timings Modes. See Table 7-158 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Input
mode for a definition of the Manual modes.
Table 7-158 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
Table 7-158. Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Input mode
BALL
AC5
AB4
F14
A19
C15
A16
A18
B19
C17
F15
AD4
AC4
AC7
AC6
AC9
AC3
AC8
AD6
AB8
AB5
B18
BALL NAME
gpio6_10
gpio6_11
mcasp1_axr15
mcasp2_aclkx
mcasp2_axr2
mcasp2_axr3
mcasp2_fsx
mcasp3_axr0
mcasp3_axr1
mcasp3_fsx
mmc3_clk
mmc3_cmd
mmc3_dat0
mmc3_dat1
mmc3_dat2
mmc3_dat3
mmc3_dat4
mmc3_dat5
mmc3_dat6
mmc3_dat7
mcasp3_aclkx
PR2_PRU0_DIR_IN_MANUAL2
A_DELAY (ps)
G_DELAY (ps)
1000
3300
1000
3400
0
1300
0
800
0
1900
0
1400
0
1400
0
1400
0
1000
0
1300
1000
3700
1000
3500
1000
3500
1000
4000
1000
3300
1000
3900
1000
3500
1000
3600
1000
3500
1000
3100
0
0
CFG REGISTER
CFG_GPIO6_10_IN
CFG_GPIO6_11_IN
CFG_MCASP1_AXR15_IN
CFG_MCASP2_ACLKX_IN
CFG_MCASP2_AXR2_IN
CFG_MCASP2_AXR3_IN
CFG_MCASP2_FSX_IN
CFG_MCASP3_AXR0_IN
CFG_MCASP3_AXR1_IN
CFG_MCASP3_FSX_IN
CFG_MMC3_CLK_IN
CFG_MMC3_CMD_IN
CFG_MMC3_DAT0_IN
CFG_MMC3_DAT1_IN
CFG_MMC3_DAT2_IN
CFG_MMC3_DAT3_IN
CFG_MMC3_DAT4_IN
CFG_MMC3_DAT5_IN
CFG_MMC3_DAT6_IN
CFG_MMC3_DAT7_IN
CFG_MCASP3_ACLKX_IN
MUXMODE
12
pr2_pru0_gpi0
pr2_pru0_gpi1
pr2_pru0_gpi20
pr2_pru0_gpi18
pr2_pru0_gpi16
pr2_pru0_gpi17
pr2_pru0_gpi19
pr2_pru0_gpi14
pr2_pru0_gpi15
pr2_pru0_gpi13
pr2_pru0_gpi2
pr2_pru0_gpi3
pr2_pru0_gpi4
pr2_pru0_gpi5
pr2_pru0_gpi6
pr2_pru0_gpi7
pr2_pru0_gpi8
pr2_pru0_gpi9
pr2_pru0_gpi10
pr2_pru0_gpi11
pr2_pru0_gpi12
Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU0 IOSET1
Direct Output mode. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO
Timings Modes. See Table 7-159 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET1 Direct Output
mode for a definition of the Manual modes.
Table 7-159 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
Table 7-159. Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET1 Direct Output mode
BALL
D7
BALL NAME
vout1_d10
PR2_PRU0_DIR_OUT_MANUAL1
A_DELAY (ps)
G_DELAY (ps)
0
600
CFG REGISTER
CFG_VOUT1_D10_OUT
MUXMODE
13
pr2_pru0_gpo7
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Timing Requirements and Switching Characteristics 345
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