AM5718_16 Datasheet, PDF (177/394 Pages) Texas Instruments – Sitara Processors Silicon Revision 2.0

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AM5718, AM5716
SPRS957C – MARCH 2016 – REVISED NOVEMBER 2016
- vdda_rtc can be combined with vdds18v
- vdd_rtc can be combined with vdd
- vddshv5 can be combined with other 1.8V or 3.3V vddshvn rails.
If combinations listed above are not followed then sequencing for these 3 voltage rails should follow the RTC mode timing requirements.
When using RTC mode timing:
- vdda_rtc rises coincident with, or before, the 1.8V interface supplies (such as vdds18v).
- vdd_rtc rises coincident with vdd, or it may rise earlier. If rising earlier, it must rise after the 1.8V interface supplies.
- vddshv5 rises coincident with the other vddshvn rails (of the same voltage) or it can rise about the same time as the 1.8V PHY
supplies (such as vdd_usb1).
(4) vdd must ramp before or at the same time as vdd_mpu, vdd_gpu, vdd_dsp and vdd_iva.
(5) vdd_mpu, vdd_gpu, vdd_dsp, vdd_iva can be ramped at the same time or can be staggered.
(6) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
(7) vddshv8 is separated out to show support for dual voltage. If single voltage is used then vddshv8 can be combined with other vddshvn
rails but vddshv8 must ramp after vdd.
(8) vdds and vdda rails must not be combined together, with the one exception of vdda_rtc when RTC-mode is not supported.
(9) Pulse duration: rtc_porz must remain low 1ms after vdda_rtc, vddshv5, and vdd_rtc are ramped and stable.
(10) The SYS_32K source must be stable and at a valid frequency 1ms prior to de-asserting rtc_porz high.
(11) Pulse duration: resetn/porz must remain low a minimum of 12P⁽¹⁵⁾ after xi_osc0 is stable and at a valid frequency. resetn/porz must
also remain low until all supply rails are valid and stable.
(12) Setup time: sysboot[15:0] pins must be valid 2P⁽¹⁵⁾ before porz is de-asserted high.
(13) Hold time: sysboot[15:0] pins must be valid 15P⁽¹⁵⁾ after porz is de-asserted high.
(14) resetn to rstoutn delay is 2ms.
(15) P = 1/(SYS_CLK1/610) frequency in ns.
(16) ddr1_vref0 may rise coincident with vdds_ddr1 or at a later time. However, it must be valid before porz rising.
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Specifications 177