AM5718_16 Datasheet, PDF (295/394 Pages) Texas Instruments – Sitara Processors Silicon Revision 2.0

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AM5718, AM5716
SPRS957C – MARCH 2016 – REVISED NOVEMBER 2016
In Table 7-76 are presented the specific groupings of signals (IOSET) for use with GMAC RMII signals.
SIGNALS
RMII_MHZ_50_CLK
rmii1_txd1
rmii1_txd0
rmii1_rxd1
rmii1_rxd0
rmii1_rxer
rmii1_txen
rmii1_crs
rmii0_txd1
rmii0_txd0
rmii0_rxd1
rmii0_rxd0
rmii0_txen
rmii0_rxer
rmii0_crs
Table 7-76. GMAC RMII IOSETs
BALL
U3
V5
V4
W9
V9
Y1
U5
V2
IOSET1
MUX
0
2
2
2
2
2
2
2
BALL
U3
IOSET2
MUX
0
Y2
1
W2
1
V6
1
U6
1
V3
1
U7
1
V7
1
Manual IO Timings Modes must be used to guaranteed some IO timings for GMAC. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-77 Manual
Functions Mapping for GMAC RMII0 for a definition of the Manual modes.
Table 7-77 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
BALL
U3
U6
V6
U7
V7
Table 7-77. Manual Functions Mapping for GMAC RMII0
BALL NAME
RMII_MHZ_50_CLK
rgmii0_txd0
rgmii0_txd1
rgmii0_txd2
rgmii0_txd3
GMAC_RMII0_MANUAL1
A_DELAY
(ps)
G_DELAY
(ps)
0
0
2444
804
2453
981
2356
847
2415
993
CFG REGISTER
MUXMODE
0
1
CFG_RMII_MHZ_50_CLK_IN
CFG_RGMII0_TXD0_IN
CFG_RGMII0_TXD1_IN
CFG_RGMII0_TXD2_IN
CFG_RGMII0_TXD3_IN
RMII_MHZ_50_CLK
rmii0_rxd0
rmii0_rxd1
rmii0_rxer
rmii0_crs
Manual IO Timings Modes must be used to guaranteed some IO timings for GMAC. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-78 Manual
Functions Mapping for GMAC RMII1 for a definition of the Manual modes.
Table 7-78 list the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
BALL
U3
V9
W9
Table 7-78. Manual Functions Mapping for GMAC RMII1
BALL NAME
RMII_MHZ_50_CLK
rgmii0_txctl
rgmii0_txc
GMAC_RMII1_MANUAL1
A_DELAY
(ps)
G_DELAY
(ps)
0
0
2450
909
2327
926
CFG REGISTER
MUXMODE
0
2
CFG_RMII_MHZ_50_CLK_IN
CFG_RGMII0_TXCTL_IN
CFG_RGMII0_TXC_IN
RMII_MHZ_50_CLK
rmii1_rxd0
rmii1_rxd1
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Timing Requirements and Switching Characteristics 295
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