TMS320TCI6486 Datasheet, PDF (34/268 Pages) Texas Instruments – TMS320TCI6486 Communications Infrastructure Digital Signal Processor

TMS320TCI6486
SPRS300N – FEBRUARY 2006 – REVISED JULY 2011
www.ti.com
Table 2-5. Terminal Functions (continued)
SIGNAL
NAME
TYPE⁽¹⁾ IPD/IPU^{(2) (3)}
NO.
DESCRIPTION
UXDATA0
G25
UXDATA1
F26
UXDATA2
E27
UXDATA3
H25
UXDATA4
G26
UXDATA5
F27
UXDATA6
E28
UXDATA7
UXDATA8
E29
O/Z
J25
IPD
UTOPIA 16-bit transmit data bus (also supports 8-bit mode on
pins [7:0])
UXDATA9
H26
UXDATA10
G27
UXDATA11
F28
UXDATA12
G28
UXDATA13
H28
UXDATA14
J27
UXDATA15
H29
UXENB
AA26
I
UTOPIA transmit interface enable input signal. Asserted by the
IPU
Master ATM Controller to indicate that the UTOPIA slave should
transmit one or more cells on the UXDATA bus with UXSOC
active on the first data cycle.
UXSOC
F29
O/Z
Transmit start-of-cell signal. This signal is output by the UTOPIA
IPD
Slave on the rising edge of the UXCLK, indicating that the first
valid byte of the cell is available on the 16-bit Transmit Data Bus
(UXDATA[15:0]).
MANAGEMENT DATA INPUT/OUTPUT (MDIO)
GMDIO
AH10
I/O/Z
IPU
MDIO serial data input/output. Only active if MACSEL0[2:0] is any
value but 011 (RGMII).
GMDCLK
AG9
O/Z
IPU
MDIO serial clock output. Only active if MACSEL0[2:0] is any
value but 011 (RGMII).
RGMDIO
AG18
I/O
MDIO serial data input/output. Only active if MACSEL0[2:0] = 011
(RGMII).
RGMDCLK
AF18
O
MDIO serial clock output. Only active if MACSEL0[2:0] = 011
(RGMII).
ETHERNET MAC (EMAC0 and EMAC1) (MII0/GMII0/RMII[1:0]/S3MII[1:0])
MRXD00/RMRXD00/SRXD0
AH11
I
EMAC Receive Data 0 (MRXD0) for MII0 [default], GMII0 and
IPU
RMII0 or Receive Data (RXD) for S3MII0. Pin function defined by
MACSEL0[2:0] (see Table 3-1).
MRXD01/RMRXD01/SRXSYNC0 AG12
I
EMAC Receive Data 1 (MRXD1) for MII0 [default], GMII0 and
IPU
RMII0 or Receive Sync (RXSYNC) for S3MII0. Pin function
defined by MACSEL0[2:0] (see Table 3-1).
MRXD02/SRXD1
AJ11
I
EMAC Receive Data 2 (MRXD2) for MII0 [default] and GMII0 or
IPU
Receive Data (RXD) for S3MII1. Pin function defined by
MACSEL0[2:0] and MACSEL1[1:0] (see Table 3-1).
MRXD03/SRXSYNC1
AJ10
I
EMAC Receive Data 3 (MRXD3) for MII0 [default] and GMII0 or
IPU
Receive Sync (RXSYNC) for S3MII1. Pin function defined by
MACSEL0[2:0] and MACSEL1[1:0] (see Table 3-1).
MRXD04/RMRXD10
AH9
I
EMAC Receive Data 4 (MRXD4) for GMII0 or Receive Data 0
IPU
(RXD0) for RMII1. Pin function defined by MACSEL0[2:0] and
MACSEL1[1:0] (see Table 3-1).
MRXD05/RMRXD11
AG7
I
EMAC Receive Data 5 (MRXD5) for GMII0 or Receive Data 1
IPU
(RXD1) for RMII1. Pin function defined by MACSEL0[2:0] and
MACSEL1[1:0] (see Table 3-1).
34
Device Overview
Copyright © 2006–2011, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s) :TMS320TCI6486